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Physical Compact Model for Source-Gated Transistors for DC Application (2025)

First Author: Golec P

Attributed to: A new low-complexity paradigm for analogue computation and hardware learning funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/ted.2024.3523885

Publication URI: http://dx.doi.org/10.1109/ted.2024.3523885

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Electron Devices