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PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model (2024)

First Author: Zhang A

Attributed to: Dijkstra's Pipe: Timing-Secure Processors by Design funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1145/3656019.3676889

Publication URI: http://dx.doi.org/10.1145/3656019.3676889

Type: Conference/Paper/Proceeding/Abstract