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Co-Design of Algorithm and FPGA Accelerator for Conditional Independence Test (2023)

First Author: Guo C

Attributed to: Event-based parallel computing - partially ordered event-triggered systems (POETS) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/asap57973.2023.00028

Publication URI: http://dx.doi.org/10.1109/asap57973.2023.00028

Type: Conference/Paper/Proceeding/Abstract

ISSN: 2160052X 21600511