Structure-Based Deadlock Checking of Asynchronous Circuits (2011)

First Author: Ren H
Attributed to:  VERification-Driven Asynchronous Design (VERDAD) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1007/s11390-011-1199-3

Publication URI: http://dx.doi.org/10.1007/s11390-011-1199-3

Type: Journal Article/Review

Parent Publication: Journal of Computer Science and Technology

Issue: 6