Signal transition graph decomposition: internal communication for speed independent circuit implementation (2011)

First Author: Wist D
Attributed to:  VERification-Driven Asynchronous Design (VERDAD) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1049/iet-cdt.2010.0162

Publication URI: http://dx.doi.org/10.1049/iet-cdt.2010.0162

Type: Journal Article/Review

Parent Publication: IET Computers & Digital Techniques

Issue: 6