A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths (2010)

First Author: Toms W
Attributed to:  VERification-Driven Asynchronous Design (VERDAD) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/acsd.2010.29

Publication URI: http://dx.doi.org/10.1109/acsd.2010.29

Type: Conference/Paper/Proceeding/Abstract

ISBN: 978-1-4244-7266-6