Logic Decomposition of Asynchronous Circuits Using STG Unfoldings (2011)

First Author: Khomenko V
Attributed to:  VERification-Driven Asynchronous Design (VERDAD) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/async.2011.10

Publication URI: http://dx.doi.org/10.1109/async.2011.10

Type: Conference/Paper/Proceeding/Abstract

ISBN: 978-1-61284-973-7