Design metrics for RTL level estimation of delay variability due to intradie (random) variations (2010)
Attributed to:
Meeting the design challenges of the nano-CMOS electronics
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/iscas.2010.5537133
Publication URI: http://dx.doi.org/10.1109/iscas.2010.5537133
Type: Conference/Paper/Proceeding/Abstract
ISBN: 978-1-4244-5308-5