High Tolerance to Gate Misalignment in Low Voltage Gate-Underlap Double Gate MOSFETs (2008)
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/led.2008.920281
Publication URI: http://dx.doi.org/10.1109/led.2008.920281
Type: Journal Article/Review
Parent Publication: IEEE Electron Device Letters
Issue: 5