Formal modelling and transformations of processor instruction sets (2011)

First Author: Mokhov A
Attributed to:  VERification-Driven Asynchronous Design (VERDAD) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/memcod.2011.5970510

Publication URI: http://dx.doi.org/10.1109/memcod.2011.5970510

Type: Conference/Paper/Proceeding/Abstract

ISBN: 978-1-4577-0117-7