Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders (2013)
Attributed to:
Channel Decoder Architectures for Energy-Constrained Wireless Communication Systems: Holistic Approach
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/wcnc.2013.6555268
Publication URI: http://dx.doi.org/10.1109/wcnc.2013.6555268
Type: Conference/Paper/Proceeding/Abstract
ISBN: 978-1-4673-5938-2