Redundant Logic Insertion and Latency Reduction in Self-Timed Adders (2012)

First Author: Balasubramanian P
Attributed to:  VERification-Driven Asynchronous Design (VERDAD) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1155/2012/575389

Publication URI: http://dx.doi.org/10.1155/2012/575389

Type: Journal Article/Review

Parent Publication: VLSI Design