Fault-tolerance techniques for hybrid CMOS/nanoarchitecture (2010)
Attributed to:
Electronics Design
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1049/iet-cdt.2008.0146
Publication URI: http://dx.doi.org/10.1049/iet-cdt.2008.0146
Type: Journal Article/Review
Parent Publication: IET Computers & Digital Techniques
Issue: 3