BIST for Intelligent Self-Testing of Integrated Circuits at Manufacture and In-Life
Lead Participant:
ATEEDA LIMITED
Abstract
The global semiconductor industry faces major challenges in testing data converters – ADCs and DACs –occupying R&D resources and constraining release of highest specification products. ATEEDA has demonstrated (via a recently completed SMART feasibility study) a new approach to Built-In Self-Test (BIST) for ADCs and DACs in simulation. Two core innovations are now patent-pending, permitting high-precision (e.g. audio) converter BIST. ATEEDA will work with Lancaster University to mitigate technical risks and validate in silicon that this approach meets commercial requirements. The resultant demonstrator will give customers confidence that this will translate into a manufacturing environment, enabling commercial evaluation and purchase. High-precision Analogue BIST is a significant market opportunity ATEEDA is well positioned to exploit following successful completion of this project, but where the risks are too high to justify development otherwise.
Lead Participant | Project Cost | Grant Offer |
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ATEEDA LIMITED | £400,320 | £ 240,192 |
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Participant |
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LANCASTER UNIVERSITY | ||
LANCASTER UNIVERSITY | £95,189 | £ 95,189 |
People |
ORCID iD |