Nanoelectronic circuits and devices
Lead Research Organisation:
University of Surrey
Department Name: ATI Electronics
Abstract
This project is based on development of new device structures, which offer improvements in performance over existing field effect transistor (FET) and source gated transistor (SGT) technology for flexible and large area electronics.
In order to demonstrate the advantages of the new structure, comparisons are required for characterisation, performance and their use in circuits.
Validation of previously run TCAD simulation data requires fabrication of devices with a well-known, cost-effective, air-stable process. Therefore, solution processed InGaZnO (IGZO) is a promising semiconductor. Devices have been fabricated within the ATI using photolithography for feature patterning, along with ebeam evaporation of electrode metals and spin-coating of IGZO, as well as the commercially available insulator, CYTOP. Early measurements show that the key to successfully creating operational devices would be the engineering of a potential energy barrier between the source contact and IGZO interface. Characterisation of the interface requires the fabrication of doides using the contact metal and semiconductor. Once a barrier can be reliably established, full devices can be produced.
Additional device development is currently underway with collaborative partnerships between universities (Cambridge with vacuum deposited IGZO, NWU with organic semiconductor), research facilities (CNR-IMM with polysilicon) and industry (Neudrive with organic semiconductor). All of which require a process for the potential energy barrier at the interface.
TCAD simulation of devices, as well as circuits, is performed to validate design ideas and develop new concepts, and have the advantage of minimal downtime. As such, their priority is changed to suit equipment availability.
Circuits can be created with existing SGTs using wedge bonding. These circuits provide an opportunity to explore the benefits of SGTs, resulting in both new discoveries and providing a benchmark for circuit function/performance with new device architectures, once fabricated.
In order to demonstrate the advantages of the new structure, comparisons are required for characterisation, performance and their use in circuits.
Validation of previously run TCAD simulation data requires fabrication of devices with a well-known, cost-effective, air-stable process. Therefore, solution processed InGaZnO (IGZO) is a promising semiconductor. Devices have been fabricated within the ATI using photolithography for feature patterning, along with ebeam evaporation of electrode metals and spin-coating of IGZO, as well as the commercially available insulator, CYTOP. Early measurements show that the key to successfully creating operational devices would be the engineering of a potential energy barrier between the source contact and IGZO interface. Characterisation of the interface requires the fabrication of doides using the contact metal and semiconductor. Once a barrier can be reliably established, full devices can be produced.
Additional device development is currently underway with collaborative partnerships between universities (Cambridge with vacuum deposited IGZO, NWU with organic semiconductor), research facilities (CNR-IMM with polysilicon) and industry (Neudrive with organic semiconductor). All of which require a process for the potential energy barrier at the interface.
TCAD simulation of devices, as well as circuits, is performed to validate design ideas and develop new concepts, and have the advantage of minimal downtime. As such, their priority is changed to suit equipment availability.
Circuits can be created with existing SGTs using wedge bonding. These circuits provide an opportunity to explore the benefits of SGTs, resulting in both new discoveries and providing a benchmark for circuit function/performance with new device architectures, once fabricated.
Organisations
Publications
Bestelink E
(2021)
Suppression of Hot-Carrier Effects Facilitated by the Multimodal Thin-Film Transistor Architecture (Adv. Electron. Mater. 9/2021)
in Advanced Electronic Materials
Bestelink E
(2021)
The Secret Ingredient for Exceptional Contact-Controlled Transistors
in Advanced Electronic Materials
Bestelink E
(2020)
Versatile Thin-Film Transistor with Independent Control of Charge Injection and Transport for Mixed Signal and Analog Computation
in Advanced Intelligent Systems
Bestelink E
(2019)
Turn-off mechanisms in thin-film source-gated transistors with applications to power devices and rectification
in Applied Physics Letters
Bestelink E
(2020)
Total Gain Recovery in Floating Gate Thin-Film Transistors for Neuromorphic and Edge Computing
in ECS Meeting Abstracts
Drury R
(2019)
Simulation Study of Overlap Capacitance in Source-Gated Transistors for Current-Mode Pixel Drivers
in IEEE Electron Device Letters
Bestelink E
(2020)
Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors
in IEEE Sensors Journal
Bestelink E
(2021)
Contact Doping as a Design Strategy for Compact TFT-Based Temperature Sensing
in IEEE Transactions on Electron Devices
Bestelink E
(2021)
Compact Unipolar XNOR/XOR Circuit Using Multimodal Thin-Film Transistors
in IEEE Transactions on Electron Devices
Surekcigil Pesch I
(2022)
Multimodal transistors as ReLU activation functions in physical neural network classifiers
in Scientific Reports