Semi-insulating Silicon substrates for high frequency integrated circuits

Lead Research Organisation: University of Southampton
Department Name: Electronics and Computer Science


Semi-insulating silicon substrates would be very attractive as handle wafers in Silicon On Insulator (SOI) technologies because they would provide very low-absorption substrates for RF and monolithic microwave integrated circuits. Two of the investigators have previously theoretically analysed the effect of different deep level impurities on silicon resistivity and shown that a resistivity of nearly should be achievable by dopant compensation. This theoretical work has been supported by our recently published experimental feasibility study that has delivered a very promising resistivity value of using Mn as the deep level impurity. This proposal aims to study the science and engineering of high resistivity silicon substrates for high frequency integrated circuits. The team encompasses expertise on the materials science of deep level impurities (University of Oxford), on the physics and technology of high frequency silicon devices (University of Southampton), on silicon wafer growth (MEMC) and on the design and fabrication of high frequency integrated circuits (Zarlink). The project aims to better understand the diffusion and doping vs resistivity relations of appropriate deep level impurities (including Mn), and hence to maximise the resistivity of the silicon handle wafer. Contamination issues arising from the deep level impurities will be addressed by investigating diffusion barriers and also by developing a back-end processing approach that takes advantage of the high diffusivity of some deep level impurities. The recent incorporation of Cu metallization into back-end silicon production processes suggests that other deep level impurities would not be seen by industry as a major contamination issue in back-end processing. Finally, SOI wafers will be fabricated on semi-insulating silicon substrates and detailed high frequency characterisation carried out.
Description We have demonstrate the ability of deep level doping to reduce the substrate losses in coplanar waveguides
and spiral inductors. Room temperature resistivity of
Au doped Czochralski-Si increases from 50 Ohmcm for n-type
Si to 100 kOhmcm for Au doped Si and temperature dependent Hall measurements show a six order increase in resistivity at lower temperatures which is entirely due to a decrease in free carrier concentration. The mobility is not affected and is determined by lattice scattering only. The resistivity follows theoretical models demonstrating that nearly 100% of the doped Au is electrically active. Coplanar waveguides show a reduction in attenuation at 67GHz from 0.88 dB/mm to 0.30 dB/mm. Spiral inductors fabricated in the compensated substrates show a 50% improvement in quality-factor with respect to high resistivity float zone wafers demonstrating the use of these substrates for integrated passive devices.
Exploitation Route patent pending
Sectors Electronics

Description University of Southampton
Amount £23,000 (GBP)
Funding ID Knowledge Transfer Secondments 
Organisation University of Southampton 
Sector Academic/University
Country United Kingdom
Start 07/2011 
End 08/2012