Globally Asynchronous Elastic Logic Synthesis (GAELS)

Lead Research Organisation: University of Manchester
Department Name: Computer Science

Abstract

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Description The objective was to prototype an automated method of partitioning an electronic circuit design in a novel - and potentially beneficial way. The development of automated tools allows a designer greater freedom to explore and thus produce designs which are better optimised for particular goals. For most conventionally produced code an automated mechanism for identifying parts of a design which can be grouped together but separated from each other 'elastically' has been achieved; partitioning may occur in ways unexpected by the original designer.

In addition some work on asynchronous interconnection - to link elastic blocks - and fault tolerance has produced some results which may assist with on-chip interconnection.
Exploitation Route Both tools and the published ideas generated may be of benefit in optimising future microelectronics designs for performance or power consumption optimisation.

Technology has been adopted in a commercial start-up venture.
Sectors Digital/Communication/Information Technologies (including Software),Electronics
URL https://github.com/balangs/eTeak
 
Description While early for looking at further impact the results may facilitate future systems-on-silicon being more capable and, in particular, more power efficient. The research work is now being used as core technology for a start-up company (Reconfigure.io).
First Year Of Impact 2016
Sector Digital/Communication/Information Technologies (including Software),Electronics
 
Title The eTeak Synthesis Framework 
Description This is eTeak. A synchronous/asycnhronous synthesis backend for the CSP-based language of Balsa. eTeak inherits the following from its predecessor system, Teak: A synthesiser from Balsa to Teak component networks A mechanism to plot those networks A language-level simulator for Balsa A programmable peephole optimiser for component networks A GUI to drive and visualise optimisation choices A prototype `back end' to generate Verilog gate-level implementations of Teak components What's new about eTeak: A Synchronous Elastic Dataflow backend for Balsa language Adopts Synchronous Elastic Protocol (SELF) Supports Synchronous, Asynchronous and Elastic protocols towards GALS synthesis Inherits a powerful visualisation engine from Teak to visualise synchronous and mixed signal interactions Supports De-Elastisation (From Asynchrony to Synchrony) and De-Synchronisation (From Synchrony to Asynchrony) Fast growing collaboration between Academia and Industry Despite the fact that there are many High-Level Synthesis tools developed in Academia and Industry, just a handful of them provide the source code for the researchers including LegUP and Chisel (which has been rebranded from a HLS tool to a HDL flow suitable for constructing large-scale hardware). eTeak is the first open-source framework that exploits asynchronous synthesis techniques to realise fine-grained synchronous circuits capable of running at different clock frequencies. 
Type Of Technology Software 
Year Produced 2015 
Open Source License? Yes  
Impact Ongoing attempts at commercialisation. 
URL https://github.com/balangs/eTeak
 
Company Name RECONFIGURE.IO LIMITED 
Description Reconfigure.io is attempting to enable the eTeak compilation technology in the FPGA based clouds. 
Year Established 2015 
Impact Currently mothballed, awaiting market opportunity.
Website http://docs.reconfigure.io/