Communication Centric Microelectronic Design
Lead Research Organisation:
University of Cambridge
Department Name: Computer Science and Technology
Abstract
We wish to undertake research into communication centricmicroelectronic design methods which are in contrast to today'scomputation centric (or gate-level) techniques. We believe thatthis research is timely since electronics is at the cusp of change.For the last 60 years, digital gates have been costly to produce andhave limited performance. We are now entering an era where the wires,which were once almost free, becoming the cost and performancelimiter. This trend is well documented in the InternationalTechnology Roadmap for Semiconductors (ITRS) roadmap which clearlyidentifies the step change needed in circuits and associated designtechniques. They also identify spiralling design complexity,escalating power densities and associated thermal problems.We believe that networks-on-chip resolve many of the design challengesfor future nano CMOS implementation technologies. Our backgroundresearch in this area has already resulted in a low latencynetwork-on-chip architecture which we have fabricated on 180nm CMOS.This initial work focused on interconnect between a tiled processorarchitecture which we have been developing with MIT. However, forthis project we wish to go much further, looking at communication atmany levels and for a range of technologies, from ASIC design on CMOSchips through to new field programmable gate array (FPGA)architectures. FPGA architecture is a departure from our usual lineof research, so we have been particularly grantified to receivea fully funded PhD studentship from Altera UK (one of the two biginternational FPGA companies) who will collaborate with us on thisproject.
People |
ORCID iD |
Simon Moore (Principal Investigator) | |
Robert Mullins (Co-Investigator) |
Publications
Barrow-Williams N
(2009)
A communication characterisation of Splash-2 and Parsec
Banerjee A
(2009)
An Energy and Performance Exploration of Network-on-Chip Architectures
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Banerjee A
(2009)
Flow-aware allocation for on-chip networks
D Greenfield
(2009)
Implications of Electronics Technology Trends to Algorithm Design
in The Computer Journal
Greenfield D
(2007)
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
A Banerjee
(2007)
Implications of Rent's rule for NoC design and its fault-tolerance
Hollis S
(2006)
RasP: An Area-efficient, On-chip Network
Description | We undertook research into communication centric microelectronic design methods which are in contrast to today's computation centric (or gate-level) techniques. This timely research is timely was undertaken at the cusp on change in electronics technology. For the last 60 years, digital gates have been costly to produce and have limited performance. We are now entering an era where the wires, which were once almost free, becoming the cost and performance limiter. This trend is well documented in the International Technology Roadmap for Semiconductors (ITRS) roadmap which clearly identifies the step change needed in circuits and associated design techniques. They also identify spiralling design complexity, escalating power densities and associated thermal problems. We demonstrated that networks-on-chip resolve many of the design challenges for future nano CMOS implementation technologies. Our research in this area has already resulted in a low latency network-on-chip architecture which we have fabricated on 180nm CMOS. This initial work focused on interconnect between a tiled processor architecture which we have been developing with MIT. However, for this project we wish to go much further, looking at communication at many levels and for a range of technologies, from ASIC design on CMOS chips through to new field programmable gate array (FPGA) architectures. FPGA architecture is a departure from our usual line of research, so we have been particularly gratified to receive a fully funded PhD studentship from Altera UK (one of the two big international FPGA companies) who will collaborate with us on this project. |
Exploitation Route | This work made an impact on modern network-on-chip design. |
Sectors | Digital/Communication/Information Technologies (including Software),Electronics |