Programmable embedded platforms for remote and compute intensive image processing applications

Lead Research Organisation: Heriot-Watt University
Department Name: S of Mathematical and Computer Sciences

Abstract

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Publications

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Archibald B (2018) Replicable parallel branch and bound search in Journal of Parallel and Distributed Computing

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Baisa N (2018) Long-term correlation tracking using multi-layer hybrid features in sparse and dense environments in Journal of Visual Communication and Image Representation

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Baisa N (2019) Development of a N-type GM-PHD filter for multiple target, multiple type visual tracking in Journal of Visual Communication and Image Representation

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Baisa N (2019) Multiple target, multiple type filtering in the RFS framework in Digital Signal Processing

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Baisa N.L. (2017) Long-Term correlation tracking using multi-layer hybrid features in dense environments in VISIGRAPP 2017 - Proceedings of the 12th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications

 
Description Reconfigurable hardware (Field Programmable Gate Arrays aka FPGAs) offer strong opportunities for efficient implementation of complex algorithms, in particular for image processing, but are very hard for non-experts to deploy effectively. We have elaborated an approach based in a very high level domain specific language (DSL) where the programmer may focus on expressing the algorithm and a rich toolset will then aid with mapping it to the FPGA. Our key outcomes are: a) a methodology for representation of Streaming Image Processing algorithms by dataflow abstractions, allowing code transformation and restructuring leading to improved performance on both FPGA and CPU architectures b) the RIPL DSL c) substantial exemplars across the spectrum of image processing in RIPL d) a machine assisted tool for exploring different configurations of RIPL programs driven by precise performance information e) design and implementation of a smart camera architecture f) evaluation of our approach on real-time image processing algorithms on an FPGA against traditional hand-crafted code g) dissemination to a wide academic and industrial audience h) foundation of a growing international workshop series on DSLs, now in its 4th year.
Exploitation Route Our framework for resource driven refactoring based on dataflow should be more widely applicable to other architectures (e.g. many-core CPU, GPU) and to heterogeneous platforms that combine these.
Sectors Aerospace

Defence and Marine

Digital/Communication/Information Technologies (including Software)

Electronics

Energy

Transport

URL http://rathlin.hw.ac.uk/
 
Description As part of our ongoing programme investigating the implementation of computer imaging and vision algorithms in embedded hardware, we have presented our findings in a number of collaborative industry-academia themed and knowledge transfer meetings under the auspices of the "Signal Processing for the Information Age" programme. Industrial partners include Mathworks, Seebyte, Atlas Elektronik, Cubicon, ADS, Kaon, BAE Systems, Leonardo, Thales, Qinetiq, and Roke Manor.
First Year Of Impact 2018
Sector Aerospace, Defence and Marine
 
Description Higher Education Impact Fellowship (HEIF) on low power and accelerated image processing hardware development
Amount £4,500 (GBP)
Organisation Sheffield Hallam University 
Sector Academic/University
Country United Kingdom
Start 06/2017 
End 06/2018
 
Description Match funded PhD studentship on 'Domain specific optimisations for real-time image processing on heterogeneous hardware'
Amount £143,000 (GBP)
Organisation ST Microelectronics 
Sector Private
Country Switzerland
Start 09/2019 
End 09/2022
 
Description Signal Procssing in the Information Age
Amount £4,092,207 (GBP)
Funding ID EP/S000631/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Public
Country United Kingdom
Start 06/2018 
End 03/2024