Silicon-based Fault-Tolerant Quantum Computing
Lead Research Organisation:
Quantum Motion
Department Name: Head office
Abstract
Quantum computation has just entered a new era, that of Noisy Intermediate-Scale Quantum (NISQ) technologies in which quantum processors are able to perform calculations beyond the capabilities of the world's greatest supercomputers. This remarkable achievement sets an important milestone in quantum computing (QC) and brings focus towards the ultimate goal of the QC roadmap: building a fault-tolerant quantum machine. A machine with sufficient error-free computing resources to run quantum algorithms with the potential to radically transform society. Algorithms that will help us better forecast weather and financial markets, speed up searches in unsorted databases, essential for the Big Data era, and most importantly, accelerate the pace of discovery of new materials and medicines, so relevant for the times we live in.
The most promising routes to fault-tolerant QC will require quantum error correction (QEC) to enable accurate computing despite the intrinsically noisy nature of the individual quantum bits constituting the machine. The idea is based on distributing the logical information over a number of physical qubits. As long as the physical qubits satisfy a maximum error rate (1% for the most forgiving method, the surface code) fault-tolerance can be achieved. The exact physical qubit overhead (per logical qubit) depends on the error rate but considering state-of-the-art qubit fidelities, it will likely be a figure in excess of a hundred. QEC is then expected to take the number of required physical qubits to many thousands for economically significant algorithms and to many millions for some of the more demanding quantum computing applications. Scaling is hence a generic scientific and technological challenge.
Building qubits based on the spin degree of freedom of individual electrons in silicon nanodevices offers numerous advantages over competing technologies such as the scalability of the most compact solid-state approach and the extensive industrial infrastructure of silicon transistor technology devoted to fabricating multi-billion-element integrated circuits. Besides, silicon electron spin qubits are one of the most coherent systems in nature, characteristic that has enabled demonstrating all the operational steps - initialization, control and readout - with sufficient level of precision for fault-tolerant computing. However, most of the results achieved so far come from devices fabricated in academic cleanrooms with relatively low level of reproducibility and in one- or two-qubit processors at best [Huang et al. Nature 569, 532]. But the recent demonstration of a single hole spin qubit [Maurand et al Nat Commun 7 13575] and electron spin control and readout in devices fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) platform open an opportunity to trigger a transition from lab-based proof-of-principle experiments to manufacturing qubits at scale [Gonzalez-Zalba et al, Physics World (2019)].
In the project SiFT, I will build on my pioneering work on CMOS-based quantum computing [Nat Commun 6 6084, Nat Elect 2 236, Nat Nano 14 437] to demonstrate, for the first time, all the necessary steps to run the surface code. I will target a two-dimensional qubit lattices where arbitrary quantum errors could be detected and corrected making clusters of qubits more reliable that the individual constituents. My quantum circuit designs will be manufactured in experimental and commercial silicon foundries that use very large-scale integration processes.
The project will be the steppingstone towards building in the UK a large-scale silicon-based quantum processor with sufficient error-free computational resources to make an impact on society. It will help take QC beyond NISQ into the fault-tolerant era where the computational promises of QC can be fully exploited.
The most promising routes to fault-tolerant QC will require quantum error correction (QEC) to enable accurate computing despite the intrinsically noisy nature of the individual quantum bits constituting the machine. The idea is based on distributing the logical information over a number of physical qubits. As long as the physical qubits satisfy a maximum error rate (1% for the most forgiving method, the surface code) fault-tolerance can be achieved. The exact physical qubit overhead (per logical qubit) depends on the error rate but considering state-of-the-art qubit fidelities, it will likely be a figure in excess of a hundred. QEC is then expected to take the number of required physical qubits to many thousands for economically significant algorithms and to many millions for some of the more demanding quantum computing applications. Scaling is hence a generic scientific and technological challenge.
Building qubits based on the spin degree of freedom of individual electrons in silicon nanodevices offers numerous advantages over competing technologies such as the scalability of the most compact solid-state approach and the extensive industrial infrastructure of silicon transistor technology devoted to fabricating multi-billion-element integrated circuits. Besides, silicon electron spin qubits are one of the most coherent systems in nature, characteristic that has enabled demonstrating all the operational steps - initialization, control and readout - with sufficient level of precision for fault-tolerant computing. However, most of the results achieved so far come from devices fabricated in academic cleanrooms with relatively low level of reproducibility and in one- or two-qubit processors at best [Huang et al. Nature 569, 532]. But the recent demonstration of a single hole spin qubit [Maurand et al Nat Commun 7 13575] and electron spin control and readout in devices fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) platform open an opportunity to trigger a transition from lab-based proof-of-principle experiments to manufacturing qubits at scale [Gonzalez-Zalba et al, Physics World (2019)].
In the project SiFT, I will build on my pioneering work on CMOS-based quantum computing [Nat Commun 6 6084, Nat Elect 2 236, Nat Nano 14 437] to demonstrate, for the first time, all the necessary steps to run the surface code. I will target a two-dimensional qubit lattices where arbitrary quantum errors could be detected and corrected making clusters of qubits more reliable that the individual constituents. My quantum circuit designs will be manufactured in experimental and commercial silicon foundries that use very large-scale integration processes.
The project will be the steppingstone towards building in the UK a large-scale silicon-based quantum processor with sufficient error-free computational resources to make an impact on society. It will help take QC beyond NISQ into the fault-tolerant era where the computational promises of QC can be fully exploited.
Publications
Ruffino, A.
(2021)
Integrated multiplexed microwave readout of silicon quantum dots in a cryogenic CMOS chip
in arXiv
Gonzalez-Zalba M
(2021)
Scaling silicon-based quantum computing using CMOS technology
in Nature Electronics
Cochrane, L.
(2021)
Quantum Dot-Based Parametric Amplifiers
in arXiv
Ruffino A
(2021)
A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics
in Nature Electronics
Oakes G. A.
(2022)
A quantum dot-based frequency multiplier
in arXiv e-prints
Vigneau, F.
(2022)
Probing quantum devices with radio-frequency reflectometry
in arXiv
Russell Angus
(2022)
Gate-based spin readout of hole quantum dots with site-dependent $g-$factors
in arXiv e-prints
Oakes, G.A.
(2022)
Fast high-fidelity single-shot readout of spins in silicon using a single-electron box
in arXiv
Cochrane L
(2022)
Parametric Amplifiers Based on Quantum Dots.
in Physical review letters
Cochrane Laurence
(2022)
Intrinsic Noise of the Single Electron Box
in arXiv e-prints
Crawford O
(2023)
Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity
in npj Quantum Information
De Michielis M
(2023)
Silicon spin qubits from laboratory to industry
in Journal of Physics D: Applied Physics
Vigneau F
(2023)
Probing quantum devices with radio-frequency reflectometry
in Applied Physics Reviews
Oakes G
(2023)
Fast High-Fidelity Single-Shot Readout of Spins in Silicon Using a Single-Electron Box
in Physical Review X
Russell A
(2023)
Gate-Based Spin Readout of Hole Quantum Dots with Site-Dependent g -Factors
in Physical Review Applied
Patom
(2023)
An elongated quantum dot as a distributed charge sensor
in arXiv e-prints
Lundberg T
(2024)
Non-symmetric Pauli spin blockade in a silicon double quantum dot
in npj Quantum Information
Description | - We have demonstrated for the first time a quantum operation between spins in a two qubit silicon quantum processor done in a device produced in a large scale fabrication facility. - We have developed a method to measured more than 1000 quantum devices in less than 15 min. Two orders of magnitude faster than the state-of-the-art. - We demonstrated a state-of-the-art sensor for spin qubits that is also compatible with large scale manufacturing. - We have upgraded charge sensors in silicon. They can now sense charges 500 nanometers apart from each other. This will certainly help optimise the layouts of quantum processors. - Quantum dots in silicon are not only great to host qubits but also to help generate the high frequency signal necessary to read and manipulate them. Now, we demonstrate a quantum-dot frequency multiplier with near-ideal frequency conversion up to x10. |
Exploitation Route | - We have developed methods to readout quantum devices that can be adopted by other researchers in the field to speed up their research |
Sectors | Digital/Communication/Information Technologies (including Software),Electronics |
URL | https://quantummotion.tech/news/ |
Title | Quantum processor layout |
Description | A new layout for a silicon-based quantum processor |
IP Reference | EP22201015.9 |
Protection | Patent / Patent application |
Year Protection Granted | |
Licensed | No |
Impact | The invention describes a quantum computer layout with higher qubit connectivity that the state-of-the-art |
Title | Thermometry |
Description | An integrated thermometer for milikelvin applications |
IP Reference | EP23157647.1 |
Protection | Patent / Patent application |
Year Protection Granted | |
Licensed | No |
Impact | New method to measure temperature on electronic chips |
Description | Silicon Quantum Information Processing 2022 (London) |
Form Of Engagement Activity | Participation in an activity, workshop or similar |
Part Of Official Scheme? | No |
Geographic Reach | International |
Primary Audience | Postgraduate students |
Results and Impact | Silicon Quantum Information Processing (QIP) is highly appealing due to excellent spin qubit performances and the expertise of the integrated circuit industry in device scaling. Demonstrations of long-lived, high-fidelity silicon qubits, multi-qubit gates and spin-photon coupling, are promising for the control and interconnect of QIP architectures. Recently, spin qubits in related semiconductors (e.g. germanium) have also emerged as promising implementations of scalable quantum hardware. The formidable challenge of scaling these systems to the level required for meaningful computational applications has also brought to the fore the need for robust cryo-CMOS electronics, which will enable fast control and data processing, as well as schemes to correct errors and protect against decoherence. This meeting will bring together leading researchers from the QIP communities of silicon and related semiconductors, as well as cryo-CMOS designers and engineers who are working at different layers of the "quantum stack". |
Year(s) Of Engagement Activity | 2022 |
URL | https://www.iop.org/events/silicon-quantum-information-processing-2022#gref |