Efficient Time-to- Digital Converters for Single-Photon Applications

Lead Research Organisation: University of Bristol
Department Name: Electrical and Electronic Engineering

Abstract

As the technology industry pursues ever faster computation to drive profits, it has turned its attention to the
fledgling field of Quantum Computation (QC), which promises to make some problems, which were previously
intractable, solvable in polynomial time. However, this raises some significant issues such as the degradation of
the security of traditional encryption systems, most notably the public-private key infrastructure which is based
on the intractability of factoring large numbers and underlies most of modern communications. Whereas this
method of encryption is secure under the assumption that processors are binary in nature, quantum computers
can factorise large numbers in polynomial time. To counteract this, schemes that provide informationtheoretically
secure communications, making use of quantum effects themselves, are being implemented, most
notably the algorithms classified as Quantum Key Distribution (QKD).
Alongside this, many measurement applications have also found that the application of single photons is
beneficial to the cause. For example, it has been found that range finding can be performed with higher
accuracy when single photons are emitted as opposed to a large cluster as would typically be done when using
time-of-flight methods, alongside the benefits of emitting less energy at a potentially living, or energy-sensitive
and hostile, target. Also, when emitting a single photon, subsurface scattering, which causes in near-field highprecision
measurements, becomes less of an issue.
QKD, single-photon measurements and the experiments currently being carried out to eventually realise
quantum computers all have something in common: they require high accuracy, high frequency, and preferably
low-cost timing equipment, known as a Time Interval Analyser (TIA). TIAs are essential to these applications as
they allow the observer to know the difference in time between two events with a very small uncertainty, usually
in the range of tens of picoseconds. In fact, for QKD and range finding, TIAs are important even when massproduced,
as the time-of-flight application is simply the measurement of a time interval and multiplication by the
speed of light through the medium, and the QKD application requires a TIA-like device to accurately lock on to
the incoming data clock rate and hence filter out the noise that appears in-between the windows for reception,
known as dark counts.
This project aims to advance the implementation techniques used to create TIAs, primarily by investigating and
improving upon the designs used for the most common TIA architecture - the Time-to-Digital Converter (TDC).
TDCs provide a substantial range benefit over other methods of creating TIAs, and so are the most common. By
improving their design, it is possible to make them more accurate, increase their count rate, and reduce their
cost, thereby assisting in the progression of the aforementioned technologies.
Current TDC designs make use of only a few designs: The Time-to-Analogue Converter (TAC) followed by an
Analogue-to-Digital Converter (ADC), the tapped delay line, the Vernier method, the Vernier ring, the stochastic
TDC and the hierarchical delay line. The methods all have benefits and trade-offs that makes them suitable for
different applications, for example, the TAC is generally very accurate, but also has a low count rate and
requires expensive analogue components. Similarly, the stochastic TDC is very accurate and has high
component costs, although this time in terms of silicon footprint, however, it lacks in the range department.
Conversely, the hierarchical delay line is very efficient in component usage, but suffers from lower accuracy due
to component mismatch and limits on propagation delays, which tend to result in it being supplemented with
another TDC for the lower bits of the timestamp.

Publications

10 25 50

Studentship Projects

Project Reference Relationship Related To Start End Student Name
EP/N509619/1 01/10/2016 30/09/2021
1794066 Studentship EP/N509619/1 01/10/2016 31/03/2020 Scott Hewitt Tancock
 
Description - The Digital Signal Processor (DSP) blocks present on a Field-Programmable Gate Array (FPGA) are capable of providing much smaller delays from input to output than any other fundamental component on the device (including carry chains, look-up tables and latches).
- However, the delays do not occur in order and there is a large delay at the start or end of each DSP block.
- Using a population counter, which counts the number of 1s in a binary string, the delays can be counted in an order-agnostic manner due to the population count monotonically increasing.
- By placing multiple DSP blocks in parallel with relative offsets, the large delays at the start and end can be accounted for resulting in much more consistency in the Least-Significant Bit (LSB) size.
- Using 10% of the DSP resources on a Xilinx Artix-7 200t FPGA, it is possible to achieve 5.25ps LSB resolution (LSB sizes were calculated through code density testing and then the cubic mean was taken).
- With a higher resolution, we can theoretically significantly reduce the gate width in Quantum Key Distribution (QKD) for lower dark counts, or we can improve the resolution and count rate of experimental instruments such as time interval analysers in Quantum Photonics.
Exploitation Route This research can be used directly in industry for time to digital conversion, such as that found in LIDAR devices, as well as in academia for implementing time interval analysers. The increase in resolution at a lower cost than other approaches lends directly to the increased usage of these devices. It's application in QKD is particularly notable as this may be the class of protocols by which banks communicate in a post-quantum information age.
Sectors Digital/Communication/Information Technologies (including Software),Education,Electronics