Memristor-based Reconfigurable Computer Architectures

Lead Research Organisation: University of Southampton
Department Name: Electronics and Computer Science


Modern electronics drives a shift from distributed, cloud and/or mainframe computing towards the 'edge'. To realise this vision, we need access to hardware technologies that are both energy and scale efficient. During the last decade, the introduction of Resistive Random Access Memory (RRAM), also known as memristors, has fuelled interest in extending Complementary Metal Oxide Semiconductor (CMOS) circuits capabilities. Specifically, their capacity to act as scalable, non-volatile, finely tuneable, electrically programmable resistive elements render them promising candidates for future computer architectures. Naturally, with the advent of memristors there has been a great interest in novel electronic systems inspired by nature, such as Artificial Neural Networks (ANNs). To that end, this emerging technology is considered as the catalyst for implementing reconfigurable circuits and systems capable of processing data in both binary and continuous information, such as analogue inference engines (fundamental part of ANNs) with the memristor efficiently emulating synaptic weights. Computer logic -wise, this means that we can design circuits that are applicable for dealing with both analogue and digital signal processing and more importantly bridging the different signal domains by converting digital vectors to an analogue value and vice versa. Presently, there is no extensive study of the behaviour of such circuits realised physically with real memristors. Hence, there are ample opportunities for developing novel electronic circuits for reconfigurable mixed-signal data processors in silico.
The aim of this research program is to build a memristor-enhanced reconfigurable computing system capable of performing mixed signal data processing. The system is inspired by memory and logic co-location systems, with the memristor in this specific case being the memory component that performs the logic operations as well, thus eliminating the von Neumann bottleneck found in conventional computers. The main concept explored in this PhD is the design, implementation and testing of in silico data processors capable of mapping data from one information domain to another, thus enabling the implementation of primitive memristor-based nanoscale circuits for mixed signal operation, a feature that cannot easily be implemented using only conventional transistor devices. The scope is extended to the analysis of a larger sea-of-gates system, where each gate is based on the developed primitive memristor-enhanced mixed signal circuits. Throughout this PhD project I am going to design, validate and physically implement proof-of-concept hybrid transistor-memristor circuits capable of neuro-inspired computing. The computational methodology of our proposed implementations is the enhancement of the data processing capabilities of conventional electronic circuits by incorporating memristor analogue memory components. The implementation of low-complexity, thus easily integrated in electronic design, primitive logic gates that can process information in digital and analogue is the main objective of the project. Hence, I am enabling the implementation of a new generation of analogue nano-scale circuitry accompanying conventional digital gates. An area of focus is circuits that can bridge the digital/analogue domain boundaries by mapping digital information to analogue output and vice versa. Hence, the exploitation of this type of converting logic (CL) concept, which is based on the analogue nature of memristor technology combined with conventional electronics, can be used to introduce a more holistic, thus application-wise versatile, novel memory and logic co-location computing paradigm that is power and area -efficient. Inspired by this concept, I am performing design, simulations, physical implementations and testing of such circuits and analyse their potential of being used as fundamental building blocks of future reconfigurable computer architectures.


10 25 50

Studentship Projects

Project Reference Relationship Related To Start End Student Name
EP/N509747/1 30/09/2016 29/09/2021
1922239 Studentship EP/N509747/1 06/03/2017 04/09/2020 Georgios Papandroulidakis