Deep learning for Hardware Trojan Detection

Lead Research Organisation: Queen's University of Belfast
Department Name: Electronics Electrical Eng and Comp Sci

Abstract

Context of The Research
Due to the globalisation of supply chains the design and manufacture of today's electronic devices are now distributed worldwide, for example, through the use of overseas foundries, third party intellectual property (IP) and third party test facilities. Many different untrusted entities may be involved in the design and assembly phases and therefore, it is becoming increasingly difficult to ensure the integrity and authenticity of devices. Thus, Hardware Trojans, which can cause the leakage of secret information and the malfunction of IC products, may be embedded or inserted into electronic devices by a malicious adversary. These activities raise serious security concerns.
A hardware Trojan (HT) is a malicious modification of a circuit in order to control, modify, disable, monitor or affect the operation of the circuit. HTs can be inserted into an IC at either design time, through the addition of malicious circuitry during RTL design or via malicious IP integration, or during manufacturing, through manipulation of the layout masks and varying the doping concentration. As adversaries would need access to foundries to insert Trojans during the fabrication process, the likelihood of them being inserted at design time is much higher.
Although there have been rare public reports of HTs detected in practice, in 2008 it was speculated that a critical failure in a Syrian radar may have been intentionally triggered via a hidden 'back door' inside a commercial off-the-shelf microprocessor. In 2014, DARPA launched the Supply Chain Hardware Integrity for Electronics Defense (SHIELD) program, the goal of which is to combine encryption, sensors, near-field power and communications into a microscopic-scale chip capable of being inserted into the packaging of an IC to detect tampering efforts. In 2016, a team of researchers from Germany and the US demonstrated the first successful real-world FPGA HT insertion into a commercial product.
Deep learning (DL) is a data driven Machine learning (ML) approach, where the goal is to ensure the learning algorithm is agnostic to the problem at hand, only the data changes. This type of approach is often based on Neural Network (NN) type architectures with multiple hidden layers. With advances in training algorithms and computational power, it is now possible to train vast amounts of data leading to the rapid advancements and adoption that we now see.
The proposed project seeks to investigate the application of deep learning in static HT detection.
Aims and Objectives
1. To evaluate state of the art in HT detection techniques.
2. To conduct the first comprehensive evaluation of the application of supervised and unsupervised ML and DL techniques in HT detection. In particular, clustering algorithms and auto-encoders will be evaluated for static Trojan detection.
3. To investigate the novel use of GANs for HT detection in gate-level netlists.
Research Methodology Including New Knowledge or Techniques
1. Investigation and limitations of the state of the art in HT detection techniques.
2. Experimentation on hardware platforms (FPGA) to implement the proposed detection technique and evaluate the performance of different detection techniques - e.g. through use of the Trust-HUB benchmark suite.
3. The adoption of Deep learning Techniques in Hardware Trojan Detection.
Research Areas
The project is compatible with EPSRC's Strategies and relevant to EPSRC's research areas as follow:
Artificial intelligence technologies; Microelectronic technology; Verification and correctness.
Companies or Collaborators
BAE Systems Applied Intelligence Labs (AI Labs) are collaborating via the EPSRC EP/R011494/1 research project. They will provide technical assessment and feedback on the research and will support the development of academic research papers.

Publications

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Studentship Projects

Project Reference Relationship Related To Start End Student Name
EP/N509541/1 01/10/2016 30/09/2021
1943868 Studentship EP/N509541/1 14/09/2017 31/03/2021 Shichao Yu