Memristor based FPGAs

Lead Research Organisation: University of Southampton
Department Name: Electronics and Computer Science


Abstracts are not currently available in GtR for all funded research. This is normally because the abstract was not required at the time of proposal submission, but may be because it included sensitive information such as personal details.


10 25 50

Studentship Projects

Project Reference Relationship Related To Start End Student Name
EP/N509747/1 01/10/2016 30/09/2021
2003304 Studentship EP/N509747/1 06/03/2017 05/03/2020 Georgios Papandroulidakis
Description Through this PhD research program, I designed, implemented and functionally validated proof-of-concept logic gates that can be used in building reconfigurable computing systems, such as future field programmable gate arrays (FPGAs). The system implemented in this PhD are based on emerging memory technologies, and more specifically in memristor device technology. The gates implemented are inspired by memory and logic co-location system concepts, thus computing modes inspired by the biological neural networks. The implementation was performed practically, using real memristor device components alongside conventional technologies to test the real-world potential of the proposed circuits. With the enabling force of the memristor memory technology, I was able in designing low-complexity programmable primitive circuits that can be incorporated into a sea-of-gates structure to enhance the functionality capabilities of conventional reconfigurable computers. Extensive simulations have been performed to develop a proof-of-concept systems design that can be used for mixed-signal programmable gate array. Firstly, through the introduction of computing modules that co-exist with the memory components we are eliminating the infamous von Neumann bottleneck that impedes the performance of today's conventional computers. Additionally, due to the analogue nature of the memristor memory technology, I was able to design primitive logic gates that can perform efficiently mixed-signal matrix multiplications, a cornerstone operation in many artificial neural network models and signal processing algorithms. My proof-of-concept hardware implementations, testing real memristor devices alongside conventional transistor technologies, and extensive simulation results, using state-of-art memristor models, provide confidence that these hybrid nano-scale CMOS-memristor circuit solution can be considered as ideal candidates for developing future reconfigurable computing systems.
Exploitation Route The design methodologies and the novel mixed-signal logic gates designed and validated using real hardware, can be used by future researchers as a stepping stone for developing in hardware even larger system consisting of the proposed logic gates and finding new algorithms that can be mapped efficiently in the hybrid technologies systems. This will enable the development of mixed-signal accelerators that would have the potential in greatly outperform conventional accelerators in power and area, thus building hardware that will significantly enhance the capabilities of 'edge' computing, a mode of computing that is on the rise.
Sectors Electronics