Nanoelectronic circuits and devices

Lead Research Organisation: University of Surrey
Department Name: ATI Electronics


This project is based on development of new device structures, which offer improvements in performance over existing field effect transistor (FET) and source gated transistor (SGT) technology for flexible and large area electronics.

In order to demonstrate the advantages of the new structure, comparisons are required for characterisation, performance and their use in circuits.
Validation of previously run TCAD simulation data requires fabrication of devices with a well-known, cost-effective, air-stable process. Therefore, solution processed InGaZnO (IGZO) is a promising semiconductor. Devices have been fabricated within the ATI using photolithography for feature patterning, along with ebeam evaporation of electrode metals and spin-coating of IGZO, as well as the commercially available insulator, CYTOP. Early measurements show that the key to successfully creating operational devices would be the engineering of a potential energy barrier between the source contact and IGZO interface. Characterisation of the interface requires the fabrication of doides using the contact metal and semiconductor. Once a barrier can be reliably established, full devices can be produced.

Additional device development is currently underway with collaborative partnerships between universities (Cambridge with vacuum deposited IGZO, NWU with organic semiconductor), research facilities (CNR-IMM with polysilicon) and industry (Neudrive with organic semiconductor). All of which require a process for the potential energy barrier at the interface.

TCAD simulation of devices, as well as circuits, is performed to validate design ideas and develop new concepts, and have the advantage of minimal downtime. As such, their priority is changed to suit equipment availability.
Circuits can be created with existing SGTs using wedge bonding. These circuits provide an opportunity to explore the benefits of SGTs, resulting in both new discoveries and providing a benchmark for circuit function/performance with new device architectures, once fabricated.


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Bestelink E (2020) P-195: Late-News-Poster: Data Retention in Pixel Drivers Based on Source-Gated Transistors in SID Symposium Digest of Technical Papers

Studentship Projects

Project Reference Relationship Related To Start End Student Name
EP/N509772/1 01/10/2016 30/09/2021
2079783 Studentship EP/N509772/1 02/07/2018 30/06/2022 Eva Bestelink