Low Latency Hardware Track Triggering and Searches for Long-Lived Particles with the ATLAS Detector

The High Luminosity upgrade to the LHC will ultimately increase the instantaneous luminosity and, as a consequence, the number of p-p interactions per bunch crossing will rise nearly an order of magnitude to 200. The ATLAS detector will be upgraded including a new tracking system (ITk) and planned hardware track trigger (HTT) in the data acquisition system.

The HTT must be able to process events at a rate of 1MHz for a small region (rHTT) of the detector and 100KHz for the full detector (gHTT). Therefore, high-speed processing is essential requiring the use of dedicated electronics. With this project, we will develop an optimized track pattern recognition algorithm for Intel Stratix 10 MX FPGAs and benchmark this solution against other technologies including ASICs, GPUs, and generic CPUs. Depending on the results, the project will either evolve to further the FPGA solution or transition to benchmarking the track parameter determination within an FPGA - another critical aspect of the HTT design.

The other aspect of the project is the search for new long-lived particles. Track information in the trigger is critical for the identification of a host of models. However, since track-triggered data will not be available during this project, we will focus on a search with the Run 2 and partial Run 3 ATLAS dataset which has discovery potential. Observing the decay of long-lived particles would, without a doubt, confirm the existence of physics beyond the standard model and revolutionize our understanding of the universe.