Feasibility of Novel Deca-nanometer vertical MOSFETs for low-cost Radio Frequency Application

Markets for radio frequency (RF) devices are various and cover ranges of low voltages (1.5, 3V etc.) for mobile applications. Conventionally, the devices required to build the front-end amplifiers are built within the same process as the digital CMOS circuitry which dominates the overall system realisation. The state-of the-art (SOA) CMOS processes are relatively expensive especially for lower volume production which is attractive to smaller companies and start-ups. Our proposal is to provide a high performance vertical MOSFET within a standard digital CMOS process such that the minimum feature size can be rather larger than SOA allowing a lower cost solution. The higher performance for the vMOST comes from the ease of producing a very short channel vertically using standard ion-implantation, rather than laterally which requires expensive patterning techniques (lithography). We have already shown the feasibility of a number of novel solutions to address some of the inherent propblems of vMOSTs. We believe that a high performance 0.1um vertical transistor with high gain and high operating voltage will be able to provide significant advantages for the market. Like all developments, it depends on the performance that can be achieved economically, and this is a key aim of this project. A sub- 0.1um transistor should exhibit an fT of around 100GHz and so provide useful power to over 10GHz. This would allow the replacement of GaAs and LDMOS devices in power stages of cellular and wireless LAN applications up to 5GHz. New connectivity and satellite uplink applications operate in frequencies up to 12GHz, and so the feasibility of the vertical MOSFET for this regime is a further objective.