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Low Dimensional Electronic Device Fabrication at Low Cost over Large Areas: Follow-on

Lead Research Organisation: University of Cambridge
Department Name: Engineering

Abstract

Over the last 40 years, we have seen a transformation in how we use electronic devices in our everyday lives from the emergence of home computing in the 1980s with occasional 'dial-up' connection of a single device in the home to the internet. In contrast, today we have a plethora of smart devices such as televisions, speakers, white goods, central heating and even doorbells all continuously connected to the internet through high speed broadband in addition to our mobile phones, tablets and personal computers. This trend will continue, with smart packaging, ubiquitous environmental monitoring, wearable wellbeing monitors amongst other emerging technologies becoming commonplace. The development of this 'Internet of Things' portents new manufacturing challenges. Silicon-based electronics has developed over this time based on trying to minimise the cost per transistor in electronic components such as microprocessors. In this way, microprocessors can be fabricated with billions of transistors at an affordable cost point. However, it is just not appropriate to use silicon-based electronics for all of these emerging applications because of cost, form factor, environmental and other limitations.
Large-area electronics (LAE) is the field which sees the use of new materials and processes to make electronics where the cost per unit area is minimised rather than the cost per device. Displays are perhaps the best known example of LAE, where a layer of electronics sits over an entire screen controlling the light output from each pixel, but other areas are emerging, and in particular the development of basic microprocessors, memories and logic on substrates such as flexible plastics which have radically different form factors from silicon. Also, as the cost of manufacture is much lower than for silicon-based electronics, manufacturing in the UK is a reality.
As with silicon, decreasing the physical size of LAE devices leads to performance enhancements, and these will be needed for future generations of smart technologies. but in general the cost of manufacture increases as feature size is reduced, and this makes fabrication at the nanoscale prohibitively expensive. We have been working on a patterning technique called Adhesion Lithography (A-Lith). This allows the reproducible fabrication of gaps ~10 nm in length to be formed between adjacent metal electrodes using only low resolution patterning of the metal electrodes themselves. We have published the design of a tool to do this at https://doi.org/10.17863/CAM.68204 . However, to make an electronic device such as a transistor, we need to put materials into the gap between these metal electrodes.
Nanomaterials, such as carbon nanotubes, silicon nanowires, zinc oxide nanowires and graphene, have been shown to have exceptional intrinsic electronic properties as a result of their nanostructure. However, the challenge is usually to put metal electrodes onto these materials to be able to make use of these properties.
In this work, we propose to develop the manufacturing processes to bring together A-Lith nanogap manufacture with the bottom-up growth of these nanomaterials so that they naturally grow across the nanogap to make a new generation of electronic devices at low cost. Two such 'nanomaterial-in-nanogap' devices which we will demonstrate are transistors and memristors. The former have been the building block behind traditional electronic circuits. The latter are seen as the building block behind the neuromorphic electronics of the future, where we create electronic devices which take inspiration from the synapses of the brain to operate.
This project aims to bring the manufacture of these new nanomaterial-in-nanogap devices for large-area electronics to reality.

Publications

10 25 50
 
Description This project looked to develop a new generation of nanomaterial-in-nanogap (n-i-n) electronic devices that can be fabricated at very low cost over large areas. A multitude of promising electronic nano materials have emerged in recent years including zinc oxide nanowires, carbon nanotubes and graphene. However, a major challenge is integrating these materials into a complete semiconductor device process. Very expensive techniques like e-beam lithography are frequently needed where nanomaterials are grown on a surface in an uncontrolled way, they are then located by electron microscopy, and finally e-beam lithography is used to add contacts to these materials to make a device. This is expensive, time-consuming, and ultimately not scalable. We have been developing a novel high resolution patterning technique called adhesion lithography (a-lith) which allows coplanar electrodes of dissimilar metals to be produced with a gap length of ~10 nm between the electrodes, but while using a simple photolithorphy patterning technique. This is achieved by depositing first metal on a substrate and patterning using photolithography. This metal is then coated in a self-assembled monolayer (SAM) which acts like a non-stick coating. A second metal is deposited over the first and patterned with photolithography as well. The second metal can then be selectively peeled away from above the first to leave the coplanar electrode structure. The significant novelty in this project is that we have demonstrated an ability to directly grow zinc oxide nanowires between the electrodes across the 10 nm gap. This has two major advantages. First is the removement of a need to pattern the nanomaterial. Is grows selectively where it is useful - between the metal electrodes. This means that the process is scalable to large areas. Secondly, the minimal volume of nanomaterial in the gap means that there a a very small probability of finding a defect, and so the intrinsic properties of the nanomaterial can be realised. We have shown this for ZnO nanowires and have extensively compared the resulting devices against ZnO thin films, with significant improvement in device performance demonstrated for a more simple fabrication process. This work has been published open access in ACS Appled Electronic Materials. We have been investigated memristors based on the nanogap structure and have learned learning about the challenges and opportunities that this presents. This has proved to be more challenging and therefore we have not achieved some of the stretch goals that were put into the project. However, the research opened up a new field: the physics of conduction in disordered materials at the nanoscale. In investigating the nanogaps, we looked at placing amorphous materials as well as nanomaterials in the gap between the electrodes. Disordered materials lack long-range order but do possess medium- and short-range order. In the course of this research, it became apparent that there was a lack of clarity regarding conduction in these materials when the lengths scale was in this medium-to-short range. This required revisiting our understanding of this physics with several key outcomes. The first was a new model for electronic disorder based on charge fluctuations which allowed a model to be created for the density of states on a length scale comparable with the nanogap devices. The second was the conclusion that the previous interpretation of localised states was misleading and in fact there is a more complicated distribution of overlapping localised states of varying spatial extents as a function of energy in these materials associated with band tails. The third is the consequence of this on conduction, and in particular the multiple trapping and release process that is usually cited as being dominant in these materials.
Exploitation Route This work will be of interest to companies in the semiconductor industry who wish to use nanomaterials in future generations of devices. There are two aspects to this. One is the process development: we have made significant advances in widening the adhesion lithography process to allow a very much wider range of materials as contacts. The second is in the physics of nanogap devices. This could be taken forward thought the development of new devices and processes, including by UK-based companies as there is no need to use high end semiconductor fabrication facilities.
Sectors Electronics

Energy

Manufacturing

including Industrial Biotechology

 
Description DSIT Semiconductor Technology Review
Geographic Reach National 
Policy Influence Type Contribution to a national consultation/review
Impact This work is influencing government policy on the semiconductor industry and how it is supported to maximise economic impact to the UK.
 
Title Data supporting "Revisiting multiple trapping and release charge transport in amorphous semiconductors exemplified by hydrogenated amorphous silicon" 
Description This dataset includes all the nonschematic figures and subfigures in the associated paper. It includes: 1. Fig. 2(a) in the paper: The band edge spatial fluctuation of the a-Si:H 2.5-dimension (2.5D) model developed in the prequel paper. Fig. 2(a).xls file records the data and is used to produce the spatial geometries of several representative extended and localized states in Fig. 2(b) as well as in the upper half of Fig. 5(a), (b) and (c). ***** 2. Fig. 2(c) in the paper: A semi-quantification of relaxation probability. Fig. 2(c).xls file provides the data of the multiplication of density of states (DOS) [g(E)] and the inoccupation probability [1-f(E)]. ***** 3. Fig. 2(d): The probability density function of local band edge, which is the basis of the ideal band fluctuation model in this paper. Fig. 2(d).xls is a duplication of the data of FIG. 1(e) in the prequel paper. ***** 4. Fig. 2(e): The band edge fluctuation of an ideal model developed in this paper (details, see Appendix A). Fig. 2(e).xls file records the data and is used to produce the spatial geometries of several representative extended and localized states in Fig. 2(f) as well as in the lower half of Fig. 5(a), (b) and (c). ***** 5. Fig. 6(a): The DOS result in the prequel paper. Fig. 6(a).xls is a duplication of the data of FIG. 1(d) in the prequel paper. ***** 6. Fig. 6(b): The TOF drift mobility data from previous literature and through fitting. Fig. 6(b).xls shows both the experimental raw data and the fitting data. ***** 7. Fig. A.1(b): The one-dimensional (1D) spatial variation of local band edge in the ideal model. FIG. A.1(b).xls file contains the 1D data. ********** Please also refer to the readme file for more information. The contents in this zip file and the corresponding paper are under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the authors and the published article's title, journal citation, and DOI. 
Type Of Material Database/Collection of data 
Year Produced 2025 
Provided To Others? Yes  
URL https://www.repository.cam.ac.uk/handle/1810/375370
 
Title Research data supporting "Understanding localized states in the band tails of amorphous semiconductors exemplified by a-Si:H from the perspective of excess delocalized charges" 
Description This dataset supports the nonschematic figures and subfigures in the corresponding paper. They include: 1. Fig. 1(a) in the paper: The equivalent excess delocalized charge distributions in the middle layer of the a-Si:H 2.5-dimension (2.5D) model developed in the paper. FIG. 1(a).xls file provides these 2D charge distribution data which correspond to models produced using different window dimensions of a moving average algorithm. 2. Fig. 1(b) in the paper: Fig. 1(b).xls file provides the probability density function (PDF) of charge distribution shared among the five cases in FIG. 1(a). 3. Fig. 1(c): FIG. 1(c).xls file provides the dependences of the proportion on r (a relation defined in paper text) for the five cases in Fig. 1(a). 4. Fig. 1(d): FIG. 1(d).xls file provides the calculated density of states (DOS) data using our model and their fitting to experimental DOS data obtained elsewhere (see Underpinning work statement.pdf). 5. Fig. 1(e): FIG. 1(e).xls file provides the data for the PDF of local band edge distribution in our model. 6. Fig. 1(f) - (h): FIG. 1(f)-(h).xls file contains the data for the local band edge distributions in the middle layer of the a-Si:H 2.5-dimension (2.5D) model developed in the paper. 7. Fig. 3: FIG. 3.xls file contains the data of the PDF of excess delocalized charges under the five cases in Fig. 1(a) and provides the data that describe the constraint between the two model parameters (standard deviation and window dimension) in order to achieve a good fitting of calculation to experimental DOS data. 8. Fig. 4: FIG. 4.xls file contains both the 2D and 1D electron probability density distribution of the model, which reflect the electron wave function envelope profile. 9. Fig. 7(d): FIG. 7(d).xls file contains the data that describe the relation between the volume of a state and the energy of the state as well as the data of the labeled points. 10. Fig. 8: FIG. 8.xls file provides the DOS data calculated in different trials to show the robustness of our modeling method to the initial data generating stochasticity. There is also a "Underpinning work statement.pdf" which specifies the secondary data and algorithm used in this paper. 
Type Of Material Database/Collection of data 
Year Produced 2024 
Provided To Others? Yes  
URL https://www.repository.cam.ac.uk/handle/1810/365144