Proof-of-principle proposal: Developing epitaxial graphene for nanoelectronics

Lead Research Organisation: University of Leeds
Department Name: Physics and Astronomy

Abstract

In this project we will prove the principles of fabricating graphene in a form useful for manufacturing nanoscale electronics and fabricate some simple devices. Graphene is a form of carbon discovered in the 21st century: a single two dimensional sheet of atoms in a hexagonal chickenwire array. It completes the set of carbon materials, which already had zero-dimensional (buckyballs), one-dimensional (nanotubes), and three-dimensional (graphite) members that are all formed by rolling or stacking up graphene sheets. In its simplest form it can be made by anyone / a pencil trace consists of millions of carbon flakes, and amongst the millions a few will be just one atomic sheet thick. Experiments on these flakes have shown that they have really remarkable properties, particularly for electronic components. The two-dimensional nature of the material, along with the symmetry of the lattice, means that the electrons in the graphene sheet have the same dynamics as relativistic particles such neutrinos: they are now commonly referred to as massless Dirac fermions, with a new quantum number, chirality, not possessed by free electrons. This has been shown to lead to bizarre new physics such as finite electrical conductivity without charge carriers and new versions of the quantum Hall effect. Although new nanoelectronic devices based on this novel physics offer exciting possibilities, using graphene can also make marked improvements to present day technologies. This is because it possesses the higher value of a key materials property than any other semiconductor: the mobility. A simple field effect CMOS-like transistor, using a graphene flake to form the channel, outperformed Si by more than a factor of ten. A major obstacle to achieving this is that building complex circuits from randomly placed, shaped, and sized flakes is not possible using today's planar fabrication technologies where reproducibility is key. What is needed a uniform layer of graphene coating an entire wafer that can be patterned and processed in the usual way. The most promising way to do this currently seems to be to use SiC wafers used commercially in high power electronics. A proper surface treatment in ultrahigh vacuum preferentially removes silicon atoms, and the carbon atoms that remain reconstruct themselves to form graphene. The promise of wafer-scale device-grade material offers the possibility of not just forming transistor channels out of graphene, but carving entire circuits from a single graphene sheet. At Leeds we have been working on epitaxial graphene production now for roughly a year. We have set up and tested the various surface science instruments that will be needed to show that graphene has indeed formed on the surface of our SiC wafer. Our recent efforts have concentrated on achieving the very high temperatures for the wafer in UHV that are the key step of producing the surface graphene, and after a series of improvements we are now close to reaching those needed. Once we have graphene, we shall optimize its production and start to make electronic devices from it. In this proof-of-principle project we have two main aims: to develop a reliable protocol for forming graphene on SiC wafers in a form useful for scaling up to manufacturing; and to build some simple demonstrator devices to show that this material can be processed in nanoscale devices including gates that can control a switching action. We will also begin some pilot experiments on connecting magnetic electrodes to graphene devices, with a view to preparing the ground for future projects involving spintronics in graphene/using the electron spin as well as charge to store and process information/which is potentially a very fertile area, as quantum spin states are very long lived in graphene, even at room temperature.
 
Description Ability to grow graphene on commercial SiC wafer. Transport reveals differences in layer structure that conventional surface science techniques are insensitive to.
Exploitation Route 'More than Moore' post-CMOS electronics Contacts with major international microelectronics companies including project partner
Sectors Digital/Communication/Information Technologies (including Software),Electronics

URL http://www.stoner.leeds.ac.uk
 
Description EPSRC
Amount £45,000 (GBP)
Funding ID PhD+ fellowship for Graham Creeth 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Public
Country United Kingdom
Start  
 
Description European Commission (EC)
Amount £443,000 (GBP)
Funding ID Q-NET 
Organisation European Commission 
Sector Public
Country European Union (EU)
Start  
 
Description European Commission (EC)
Amount £443,000 (GBP)
Funding ID Q-NET 
Organisation European Commission 
Sector Public
Country European Union (EU)
Start  
 
Description Intel Corporation Ltd
Amount £25,000 (GBP)
Organisation Intel Corporation 
Sector Private
Country United States
Start  
 
Description Intel Corporation Ltd
Amount £25,000 (GBP)
Organisation Intel Corporation 
Department Intel Corporation (UK) Ltd
Sector Private
Country United Kingdom
Start