Highly-parallel algorithms and architectures for high-throughput wireless receivers

Lead Research Organisation: University of Southampton
Department Name: Electronics and Computer Science

Abstract

During the past two decades, reliable wireless communication at near-theoretical-limit transmission throughputs has been facilitated by receivers that operate on the basis of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. Most famously, this algorithm is employed for turbo error correction in the Long Term Evolution (LTE) standard for cellular telephony, as well as in its previous-generation predecessors. Looking forward, turbo error correction promises transmission throughputs in excess of 1 Gbit/s, which is the goal specified in the IMT-Advanced requirements for next-generation cellular telephony standards. Throughputs of this order have only very recently been achieved by State-Of-the-Art (SOA) LTE turbo decoder implementations. However, this has been achieved by exploiting every possible opportunity to increase the parallelism of the BCJR algorithm at an architectural level, implying that the SOA approach has reached its fundamental limit. This limit may be attributed to the data dependencies of the BCJR algorithm, resulting in an inherently serial nature that cannot be readily mapped to processing architectures having a high degree of parallelism.

Against this background, we propose to redesign turbo decoder implementations at an algorithmic level, rather than at the architectural level of the SOA approach. More specifically, we have recently been successful in devising an alternative to the BCJR algorithm, which has the same error correction capability, but does not have any data dependencies. Owing to this, our algorithm can be mapped to highly-parallel many-core processing architectures, facilitating an LTE turbo decoder processing throughput that is more than an order of magnitude higher than the SOA, satisfying future demands for gigabit throughputs. We will achieve this for the first time by developing a custom Field Programmable Gate Array (FPGA) architecture, comprising hundreds of processing cores that are interconnected using a reconfigurable Benes network. Furthermore, we will develop custom Network-on-Chip (NoC) architectures that facilitate different trade-offs between chip area, energy-efficiency, reconfigurability, processing throughput and latency. In parallel to developing these high-performance custom implementation architectures, we will apply our novel algorithm to both existing Graphics Processing Unit (GPU) and NoC architectures. This will grant us a rapid pace, allowing us to apply our novel algorithm to not only error correction, but to all aspects of receiver operation, including demodulation, equalisation, source decoding, channel estimation and synchronisation. Drawing upon our high-throughput algorithms and highly-parallel processing architectures, we will develop techniques for holistically optimising the algorithmic and implementational parameters of both the transmitter and receiver. This will facilitate practical high-performance schemes, which can pave the way for future generations of wireless communication.

This research addresses key EPSRC priorities in the Information and Communication Technologies theme (http://www.epsrc.ac.uk/ourportfolio/themes/ict), including 'Many-core architectures and concurrency in distributed and embedded systems' and 'Towards an intelligent information infrastructure'. The 'Working together' priority is also addressed, since this cross-disciplinary research will develop new knowledge that spans the gap between high-performance communication theory and high-performance hardware design. This research will offer new insights into the design of many-core architectures, which the hardware design community will be able to apply in the design of general purpose architectures. Furthermore, the communication theory community will be able to apply our algorithms across even wider aspects of receiver operation.

Planned Impact

This research will enable significant economic and societal benefits, since we will closely engage with our broad range of industrial partners, helping them to develop wireless receivers with significantly improved processing throughputs. This will remove the bottleneck imposed upon the transmission throughput of wireless communication systems employing SOA components. As a broader benefit, future wireless communication systems may also employ the results of our research for SOA source decoding, demodulation, equalisation, channel estimation and synchronisation. This will facilitate the near theoretical limit exploitation of limited bandwidth, hence resulting in significant societal benefits, allowing more wireless communication services to be offered to the public. Furthermore, the proposed highly-parallel turbo decoders are compatible with the Long Term Evolution (LTE) cellular telephony standard, as well as with its predecessors and successors. Owing to this, our turbo decoders can be employed in cellular handsets and base stations throughout the world, within ten years. The UK is already a world leader in general purpose parallel processing and the proposed research will grant the UK a significant head-start in parallel processing for wireless communications, creating significant economic benefits.

The proposed research will be of significant benefit to our three industrial partners, as stated in the corresponding Letters of Support. The design of highly-parallel algorithms and architectures for high-throughput wireless receivers is of significant interest to Altera. In particular, Altera wish to engage with this research, so that they can demonstrate the suitability of their highly-parallel processing platforms to these new areas. Furthermore, this research will develop some soft Intellectual Property (IP), which Altera will market commercially. Similarly, ARM already has a significant involvement with our team through the ARM-ECS Research Centre (http://www.arm.ecs.soton.ac.uk), with a particular interest in the proposed co-design of algorithms and architectures for high-throughput wireless receivers. More specifically, ARM is already leading the world in general purpose processing architectures and they are eager to reproduce this success in wireless communication. Finally, as one of the world's leading communications services companies, BT has a significant interest in the proposed research, which will enable high-throughput wireless services. In particular, BT is an active participant in communications standardisation, offering a route for the proposed research to influence future standards.

Throughout his PhD, the named Research Assistant (RA) Shaoshi Yang has gained significant expertise in designing communication algorithms having both a high performance and a low complexity, as shown in the attached CV. This combination is highly sought after in both UK industry and academia, since it facilitates holistic design, which can yield significant benefits like those described in this proposal. The experience that the named RA and the second RA will gain from their involvement in this proposal will significantly further develop their expertise. In addition to developing the expertise of the Principal Investigator (PI), undertaking this role will further develop his project leadership skills. The experience that the PI gains from managing this work and his team will enable him to undertake even more ambitious projects in the future, having greater scope and impact. Furthermore, the liaison with academia and industry detailed in this proposal will provide valuable networking opportunities for the PI. In the future, this will provide him with further opportunities to collaborate and undertake work with broader scope and impact. Furthermore, the PhD student funded by Altera will follow in the RAs' footsteps, gaining valuable expertise in both communication algorithms and hardware design.

Publications

10 25 50
 
Description During the past two decades, reliable wireless communication at near-theoretical-limit transmission throughputs has been facilitated by receivers that operate on the basis of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. Most famously, this algorithm is employed for turbo error correction in the Long Term Evolution (LTE) standard for cellular telephony, as well as in its previous-generation predecessors. State-Of-the-Art (SOA) LTE turbo decoder implementations achieve transmission throughputs of around 2 Gbit/s, meeting the IMT-Advanced requirements for 4G cellular telephony standards. However, this has been achieved by exploiting every possible opportunity to increase the parallelism of the BCJR algorithm at an architectural level, implying that the SOA approach has reached its fundamental limit. This limit may be attributed to the data dependencies of the BCJR algorithm, resulting in an inherently serial nature that cannot be readily mapped to processing architectures having a high degree of parallelism.

Against this background, redesigned the turbo decoder implementation at an algorithmic level, rather than at the architectural level of the SOA approach. More specifically, we devised an alternative to the BCJR algorithm, which has the same error correction capability, but does not have any data dependencies. Owing to this, our algorithm can be mapped to highly-parallel many-core processing architectures, facilitating a turbo decoder processing throughput that is more than an order of magnitude higher than the SOA, satisfying the 4G requirement for 20 Gbit/s. We achieved this for the first time by developing custom Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) architectures, comprising hundreds or thousands of processing cores that are interconnected using a reconfigurable Benes network. Furthermore, we developed custom Network-on-Chip (NoC) architectures that facilitate different trade-offs between chip area, energy-efficiency, reconfigurability, processing throughput and latency. In parallel to developing these high-performance custom implementation architectures, we applied our novel algorithm to existing Graphics Processing Unit (GPU) architectures. This granted us a rapid pace, allowing us to apply our novel algorithm to not only error correction, but to all aspects of receiver operation, including demodulation and source decoding. Drawing upon our high-throughput algorithms and highly-parallel processing architectures, we developed techniques for holistically optimising the algorithmic and implementational parameters of both the transmitter and receiver. This facilitates practical high-performance schemes, which can pave the way for future generations of wireless communication.
Exploitation Route This cross-disciplinary research has developed new knowledge that spans the gap between communication theory and high-performance hardware design, opening up new areas of research in both of these fields. Our novel highly-parallel algorithms designed for State-Of-the-Art (SOA) wireless receivers have improved the associated processing throughput by more than an order of magnitude, which is necessitated for meeting the requirements of future wireless generations. While we have applied our algorithms to a wide range of applications, these still only represent a small fraction of the potential applicability, creating a huge opportunity for other researchers of diverse affiliated areas, who will be able to implement the wireless receiver components that have been proposed by the communication theory community. Furthermore, our novel highly-parallel implementations of wireless receiver components have offered new insights into the design of many-core architectures and Network-on-Chips (NoCs), which the hardware design community will be able to apply in the design of general purpose architectures. Finally, researchers with expertise in communications theory can benefit from the proposed methodologies for accurately estimating the hardware characteristics of the proposed wireless receiver components. For example, these researchers will be able to offset the reduction in transmission energy that is afforded by an SOA wireless receiver, with the energy consumption of its implementation, even if they have no particular expertise in hardware design. For the first time, our proposed methodologies have enabled the holistic design of wireless receivers, without requiring the time-consuming fabrication of the corresponding implementations. As a result, the pace and completeness of this research will be significantly improved. The research is now being commercialised by the spin-out AccelerComm and it has informed contributions to the 3GPP standardisation process for 5G telecommunications.
Sectors Digital/Communication/Information Technologies (including Software)

 
Description The research has led to the formation of the spin-out company AccelerComm and has informed the 3GPP standardisation process for 5G telecommunications.
First Year Of Impact 2016
Sector Digital/Communication/Information Technologies (including Software)
Impact Types Economic

 
Description 3GPP standardiation
Geographic Reach Multiple continents/international 
Policy Influence Type Participation in a advisory committee
Impact Contributed technical documents and way-forward proposals to the 3GPP standardisation process for 5G telecommunications
 
Description Department of Digital, Culture, Media and Sport consultation
Geographic Reach National 
Policy Influence Type Gave evidence to a government review
 
Description Aid for Startups
Amount £500,000 (GBP)
Funding ID 900037 
Organisation Innovate UK 
Sector Public
Country United Kingdom
Start 05/2016 
End 04/2018
 
Description Connected and Autonomous Vehicles
Amount £250,000 (GBP)
Organisation Innovate UK 
Sector Public
Country United Kingdom
Start 04/2018 
End 10/2019
 
Description Generalised LDPC architectures for high-throughput FPGA realisation (Altera)
Amount € 75,000 (EUR)
Organisation Altera 
Sector Private
Country United States
Start 09/2013 
End 09/2016
 
Description Generalised LDPC architectures for high-throughput FPGA realisation (UoS)
Amount £21,000 (GBP)
Organisation University of Southampton 
Sector Academic/University
Country United Kingdom
Start 09/2013 
End 09/2016
 
Description HARNet
Amount £247,333 (GBP)
Funding ID TS/L009390/1 
Organisation Innovate UK 
Sector Public
Country United Kingdom
Start 10/2013 
End 12/2015
 
Description Innovation to Commercialisation of University Research
Amount £50,000 (GBP)
Organisation SETsquared Partnership 
Sector Charity/Non Profit
Country United Kingdom
Start 10/2015 
End 03/2016
 
Description Knowledge Transfer Partnership
Amount £190,000 (GBP)
Organisation Innovate UK 
Sector Public
Country United Kingdom
Start 07/2018 
End 12/2020
 
Description PhD funding
Amount £75,000 (GBP)
Organisation Qinetiq 
Sector Private
Country United Kingdom
Start 07/2016 
End 06/2023
 
Title 3GPP New Radio polar code reference model 
Description Models the operation of the 3GPP New Radio polar code, allowing other to confirm the compliance of their solutions with the standard. 
Type Of Material Computer model/algorithm 
Year Produced 2017 
Provided To Others? Yes  
Impact Used by other companies to confirm the compliance of their solutions with the standard. 
URL https://github.com/robmaunder/polar-3gpp-matlab
 
Title FPGA implementations of LDPC decoders 
Description Database of 40 data items of 139 different FPGA implementations of LDPC decoders. 
Type Of Material Database/Collection of data 
Year Produced 2015 
Provided To Others? Yes  
Impact This database has generated a significant amount of interest and downloads from researchers around the world. 
URL http://eprints.soton.ac.uk/384946/
 
Title Survey of ASIC and FPGA implementations of polar decoders 
Description Survey of ASIC and FPGA implementations of polar decoders 
Type Of Material Database/Collection of data 
Year Produced 2016 
Provided To Others? Yes  
Impact 3GPP standardisation process influenced 
URL http://eprints.soton.ac.uk/400401/
 
Title Survey of ASIC implementations of turbo and LDPC decoders 
Description Survey of ASIC implementations of turbo and LDPC decoders 
Type Of Material Database/Collection of data 
Year Produced 2016 
Provided To Others? Yes  
Impact Influenced 3GPP standardisation process 
URL http://eprints.soton.ac.uk/399846/
 
Description 3GPP meetings 
Organisation Ericsson
Country Sweden 
Sector Private 
PI Contribution I have been representing AccelerComm at 3GPP standardisation meetings, where the error correction code for 5G mobile systems is being selected. In these meetings, I have led the consortium of companies that support the turbo code, which includes Ericsson, LG Electronics, NEC, Sony and Orange. In particular, I have presented and defended this consortium's way-forward proposals during these debates, as well as several papers of my own.
Collaborator Contribution Co-signed way-forward proposals and contributed papers.
Impact Contributed to 3GPP standard for 5G telecommunications.
Start Year 2016
 
Description 3GPP meetings 
Organisation LG Electronics
Country Korea, Republic of 
Sector Private 
PI Contribution I have been representing AccelerComm at 3GPP standardisation meetings, where the error correction code for 5G mobile systems is being selected. In these meetings, I have led the consortium of companies that support the turbo code, which includes Ericsson, LG Electronics, NEC, Sony and Orange. In particular, I have presented and defended this consortium's way-forward proposals during these debates, as well as several papers of my own.
Collaborator Contribution Co-signed way-forward proposals and contributed papers.
Impact Contributed to 3GPP standard for 5G telecommunications.
Start Year 2016
 
Description 3GPP meetings 
Organisation NEC Corporation
Department NEC (UK) Ltd
Country United Kingdom 
Sector Private 
PI Contribution I have been representing AccelerComm at 3GPP standardisation meetings, where the error correction code for 5G mobile systems is being selected. In these meetings, I have led the consortium of companies that support the turbo code, which includes Ericsson, LG Electronics, NEC, Sony and Orange. In particular, I have presented and defended this consortium's way-forward proposals during these debates, as well as several papers of my own.
Collaborator Contribution Co-signed way-forward proposals and contributed papers.
Impact Contributed to 3GPP standard for 5G telecommunications.
Start Year 2016
 
Description 3GPP meetings 
Organisation Orange France Telecom
Country France 
Sector Private 
PI Contribution I have been representing AccelerComm at 3GPP standardisation meetings, where the error correction code for 5G mobile systems is being selected. In these meetings, I have led the consortium of companies that support the turbo code, which includes Ericsson, LG Electronics, NEC, Sony and Orange. In particular, I have presented and defended this consortium's way-forward proposals during these debates, as well as several papers of my own.
Collaborator Contribution Co-signed way-forward proposals and contributed papers.
Impact Contributed to 3GPP standard for 5G telecommunications.
Start Year 2016
 
Description 3GPP meetings 
Organisation SONY
Country Japan 
Sector Private 
PI Contribution I have been representing AccelerComm at 3GPP standardisation meetings, where the error correction code for 5G mobile systems is being selected. In these meetings, I have led the consortium of companies that support the turbo code, which includes Ericsson, LG Electronics, NEC, Sony and Orange. In particular, I have presented and defended this consortium's way-forward proposals during these debates, as well as several papers of my own.
Collaborator Contribution Co-signed way-forward proposals and contributed papers.
Impact Contributed to 3GPP standard for 5G telecommunications.
Start Year 2016
 
Description 3GPP meetings 
Organisation Telecom Bretagne
Country France 
Sector Academic/University 
PI Contribution I have been representing AccelerComm at 3GPP standardisation meetings, where the error correction code for 5G mobile systems is being selected. In these meetings, I have led the consortium of companies that support the turbo code, which includes Ericsson, LG Electronics, NEC, Sony and Orange. In particular, I have presented and defended this consortium's way-forward proposals during these debates, as well as several papers of my own.
Collaborator Contribution Co-signed way-forward proposals and contributed papers.
Impact Contributed to 3GPP standard for 5G telecommunications.
Start Year 2016
 
Description ARM 
Organisation ARM Holdings
Country United Kingdom 
Sector Private 
PI Contribution We have setup a continuing dialogue with ARM about our work on the practical implementation of architectures for wireless communication processing, for the purpose of knowledge transfer.
Collaborator Contribution ARM are an industrial partner of our further funding project 'Highly-parallel algorithms and architectures for high-throughput wireless receivers'. ARM provide feedback on our research findings and help to shape our future research directions. ARM are also supporting a PhD student, who is contributing to this project.
Impact A PhD and publications are emerging from this project.
Start Year 2012
 
Description AccelerComm 
Organisation AccelerComm
Country United Kingdom 
Sector Private 
PI Contribution AccelerComm is collaborating with the University of Southampton under directly funded research collaboration agreements, Innovate UK projects and Knowledge Transfer Partnerships. The University is contributing algorithmic expertise on signal processing for 5G mobile communications.
Collaborator Contribution AccelerComm is contributing hardware implementation expertise on signal processing for 5G mobile communications.
Impact Product development. 5G standardisation contributions.
Start Year 2017
 
Description Altera 
Organisation Altera
Department Altera Europe
Country United Kingdom 
Sector Private 
PI Contribution We have setup a continuing dialogue with Altera about our work on the practical implementation of architectures for wireless communication processing, for the purposes of knowledge transfer. We are developing soft-IP on LDPC decoders for Altera.
Collaborator Contribution Altera are an industrial partner of our further funding project 'Highly-parallel algorithms and architectures for high-throughput wireless receivers'. Altera have partly funded a studentship, which will be used to develop the above-mentioned soft-IP. Altera provide feedback on our research findings and help to shape our future research directions. Altera are an industrial partner of our EPSRC fellowship application 'Holistic design of signal processing algorithms, waveforms and hardware implementations for ultra-low- latency wireless communication'
Impact A PhD, publications and soft-IP are emerging from this collaboration.
Start Year 2013
 
Description Cascoda 
Organisation Cascoda
Country United Kingdom 
Sector Private 
PI Contribution We have setup a continuing dialogue with Cascoda about our work on the practical implementation of architectures for wireless communication processing, for the purpose of knowledge transfer.
Collaborator Contribution Cascoda are an industrial partner of our EPSRC fellowship application 'Holistic design of signal processing algorithms, waveforms and hardware implementations for ultra-low- latency wireless communication'. Cascoda provide feedback on our research findings and help to shape our future research directions.
Impact Knowledge transfer has resulted from this collaboration.
Start Year 2015
 
Description Cobham 
Organisation Cobham
Country United Kingdom 
Sector Private 
PI Contribution We have setup a continuing dialogue with Cobham about our work on the practical implementation of architectures for wireless communication processing, for the purpose of knowledge transfer. We are developing algorithms which Cobham will use in their products.
Collaborator Contribution Cobham are an industrial partner of our further funding project 'HARNet'. Cobham provide feedback on our research findings and help to shape our future research directions.
Impact Publications and algorithms for Cobham's products are emerging from this collaboration.
Start Year 2014
 
Description DSTL 
Organisation Defence Science & Technology Laboratory (DSTL)
Country United Kingdom 
Sector Public 
PI Contribution DSTL are sponsoring a part-time PhD student.
Collaborator Contribution DSTL are providing co-supervision and are informing the direction of the research.
Impact PhD training has resulted from this collaboration.
Start Year 2017
 
Description Harnessing Quantum-Computing & Signal Processing in Wireless Communications 
Organisation Indian Institute of Technology Madras
Country India 
Sector Academic/University 
PI Contribution We published several joint 4* papers, which contribute to the REF;
Collaborator Contribution Deriving closed-form equations for characterizing device-to-device communications and IoT
Impact mathematics, information theory, signal processing, computer science, telecommunications engineering
Start Year 2017
 
Description McKay Brothers Microwave 
Organisation McKay Brothers Microwave
Country United States 
Sector Private 
PI Contribution We have setup a continuing dialogue with McKay Brothers Microwave about our work on the practical implementation of architectures for wireless communication processing, for the purpose of knowledge transfer.
Collaborator Contribution McKay Brothers Microwave are an industrial partner of our EPSRC fellowship application 'Holistic design of signal processing algorithms, waveforms and hardware implementations for ultra-low- latency wireless communication'. McKay Brothers Microwave provide feedback on our research findings and help to shape our future research directions.
Impact Knowledge transfer has resulted from this collaboration.
Start Year 2015
 
Description National Instruments 
Organisation National Instruments Corp (UK) Ltd
Country United Kingdom 
Sector Private 
PI Contribution We have setup a continuing dialogue with National Instruments about our work on the practical implementation of architectures for wireless communication processing, for the purpose of knowledge transfer.
Collaborator Contribution National Instruments have provided support for their software and hardware, which we use in our research. National Instruments provide feedback on our research findings and help to shape our future research directions. National Instruments are an industrial partner of our EPSRC fellowship application 'Holistic design of signal processing algorithms, waveforms and hardware implementations for ultra-low- latency wireless communication'
Impact Knowledge transfer has resulted from this collaboration.
Start Year 2012
 
Description Technische Universität Dresden 
Organisation Technical University of Dresden
Country Germany 
Sector Academic/University 
PI Contribution We have setup a continuing dialogue with TU Dresden about our work on the practical implementation of architectures for wireless communication processing, for the purpose of knowledge transfer.
Collaborator Contribution TU Dresden are an acadmic partner of our EPSRC fellowship application 'Holistic design of signal processing algorithms, waveforms and hardware implementations for ultra-low- latency wireless communication'. TD Dresden provide feedback on our research findings and help to shape our future research directions.
Impact Knowledge transfer has resulted from this collaboration.
Start Year 2015
 
Description University of Bristol 
Organisation University of Bristol
Department Department of Electrical and Electronic Engineering
Country United Kingdom 
Sector Academic/University 
PI Contribution We have setup a continuing dialogue with the University of Bristol about our work on the practical implementation of architectures for wireless communication processing, for the purpose of knowledge transfer.
Collaborator Contribution The University of Bristol is an academic partner of our EPSRC fellowship application 'Holistic design of signal processing algorithms, waveforms and hardware implementations for ultra-low- latency wireless communication'. The University of Bristol provide feedback on our research findings and help to shape our future research directions.
Impact Knowledge transfer has resulted from this collaboration.
Start Year 2015
 
Title Detection Circuit, Receiver, Communications Device and Method of Detecting 
Description This patent covers the fully-parallel turbo decoding algorithm and architecture. 
IP Reference GB2529209 
Protection Patent application published
Year Protection Granted 2016
Licensed Yes
Impact Assigned to AccelerComm
 
Title FULLY PARALLEL TURBO DECODING 
Description A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process. 
IP Reference WO2016023762 
Protection Patent application published
Year Protection Granted 2016
Licensed Yes
Impact Assigned to AccelerComm
 
Title Arbitrarily Parallel Turbo Decoder 
Description Soft IP for Arbitrarily Parallel Turbo Decoder 
Type Of Technology New/Improved Technique/Technology 
Year Produced 2017 
Impact Licensing discussions with several potential customers underway 
 
Company Name AccelerComm 
Description Soft-IP semiconductor company for hardware acceleration of wireless communication signal processing 
Year Established 2016 
Impact Raised external investment, created jobs, in licensing discussions with several potential customers
Website http://www.accelercomm.com
 
Description 3GPP standardisation 
Form Of Engagement Activity A formal working group, expert panel or dialogue
Part Of Official Scheme? No
Geographic Reach International
Primary Audience Industry/Business
Results and Impact Contributed technical documents and way-forward proposals to the 3GPP standardisation process for 5G telecommunications
Year(s) Of Engagement Activity 2016,2017
 
Description Academic presentation (University of York) 
Form Of Engagement Activity A talk or presentation
Part Of Official Scheme? No
Geographic Reach National
Primary Audience Postgraduate students
Results and Impact This talk sparked questions and discussions afterwards.

A closer relationship has been built with the University of York.
Year(s) Of Engagement Activity 2014
 
Description GC-WOC keynote 
Form Of Engagement Activity A talk or presentation
Part Of Official Scheme? No
Geographic Reach International
Primary Audience Other audiences
Results and Impact Keynote address at Global Conference on Wireless and Optical Communications
Year(s) Of Engagement Activity 2016
 
Description NIWeek Keynote 
Form Of Engagement Activity A talk or presentation
Part Of Official Scheme? No
Geographic Reach International
Primary Audience Other audiences
Results and Impact Academic keynode address at NIWeek 2016
Year(s) Of Engagement Activity 2016
URL https://youtu.be/8qqCWPj-di8
 
Description SETsquared Innovation to Commercialisation of University Research 
Form Of Engagement Activity A formal working group, expert panel or dialogue
Part Of Official Scheme? No
Geographic Reach International
Primary Audience Industry/Business
Results and Impact Engaged with over 100 individuals from companies all over the world, including EE, TMobile, China Mobile, AT&T, Rohde & Schwarz, Nokia Networks, Alcatel-Lucent, Ericsson, Samsung, Thales, Huawei, Altera, Qualcomm, National Instruments, nVidia, ARM, Imagination Technologies, Analog Devices, BAe Systems and Cobham. The aim of these engagements was to create awareness for our research outputs, to understand the problems faced by industry, to see how well our research addresses these problems and to inform our future research.
Year(s) Of Engagement Activity 2015
 
Description TU Dortmund Summer School 
Form Of Engagement Activity A talk or presentation
Part Of Official Scheme? No
Geographic Reach International
Primary Audience Postgraduate students
Results and Impact Summer school talk on joint design of algorithms and architectures for signal processing in wireless communications.
Year(s) Of Engagement Activity 2017