Low Dimensional Electronic Device Fabrication at Low Cost over Large Areas: Follow-on
Lead Research Organisation:
University of Cambridge
Department Name: Engineering
Abstract
Over the last 40 years, we have seen a transformation in how we use electronic devices in our everyday lives from the emergence of home computing in the 1980s with occasional 'dial-up' connection of a single device in the home to the internet. In contrast, today we have a plethora of smart devices such as televisions, speakers, white goods, central heating and even doorbells all continuously connected to the internet through high speed broadband in addition to our mobile phones, tablets and personal computers. This trend will continue, with smart packaging, ubiquitous environmental monitoring, wearable wellbeing monitors amongst other emerging technologies becoming commonplace. The development of this 'Internet of Things' portents new manufacturing challenges. Silicon-based electronics has developed over this time based on trying to minimise the cost per transistor in electronic components such as microprocessors. In this way, microprocessors can be fabricated with billions of transistors at an affordable cost point. However, it is just not appropriate to use silicon-based electronics for all of these emerging applications because of cost, form factor, environmental and other limitations.
Large-area electronics (LAE) is the field which sees the use of new materials and processes to make electronics where the cost per unit area is minimised rather than the cost per device. Displays are perhaps the best known example of LAE, where a layer of electronics sits over an entire screen controlling the light output from each pixel, but other areas are emerging, and in particular the development of basic microprocessors, memories and logic on substrates such as flexible plastics which have radically different form factors from silicon. Also, as the cost of manufacture is much lower than for silicon-based electronics, manufacturing in the UK is a reality.
As with silicon, decreasing the physical size of LAE devices leads to performance enhancements, and these will be needed for future generations of smart technologies. but in general the cost of manufacture increases as feature size is reduced, and this makes fabrication at the nanoscale prohibitively expensive. We have been working on a patterning technique called Adhesion Lithography (A-Lith). This allows the reproducible fabrication of gaps ~10 nm in length to be formed between adjacent metal electrodes using only low resolution patterning of the metal electrodes themselves. We have published the design of a tool to do this at https://doi.org/10.17863/CAM.68204 . However, to make an electronic device such as a transistor, we need to put materials into the gap between these metal electrodes.
Nanomaterials, such as carbon nanotubes, silicon nanowires, zinc oxide nanowires and graphene, have been shown to have exceptional intrinsic electronic properties as a result of their nanostructure. However, the challenge is usually to put metal electrodes onto these materials to be able to make use of these properties.
In this work, we propose to develop the manufacturing processes to bring together A-Lith nanogap manufacture with the bottom-up growth of these nanomaterials so that they naturally grow across the nanogap to make a new generation of electronic devices at low cost. Two such 'nanomaterial-in-nanogap' devices which we will demonstrate are transistors and memristors. The former have been the building block behind traditional electronic circuits. The latter are seen as the building block behind the neuromorphic electronics of the future, where we create electronic devices which take inspiration from the synapses of the brain to operate.
This project aims to bring the manufacture of these new nanomaterial-in-nanogap devices for large-area electronics to reality.
Large-area electronics (LAE) is the field which sees the use of new materials and processes to make electronics where the cost per unit area is minimised rather than the cost per device. Displays are perhaps the best known example of LAE, where a layer of electronics sits over an entire screen controlling the light output from each pixel, but other areas are emerging, and in particular the development of basic microprocessors, memories and logic on substrates such as flexible plastics which have radically different form factors from silicon. Also, as the cost of manufacture is much lower than for silicon-based electronics, manufacturing in the UK is a reality.
As with silicon, decreasing the physical size of LAE devices leads to performance enhancements, and these will be needed for future generations of smart technologies. but in general the cost of manufacture increases as feature size is reduced, and this makes fabrication at the nanoscale prohibitively expensive. We have been working on a patterning technique called Adhesion Lithography (A-Lith). This allows the reproducible fabrication of gaps ~10 nm in length to be formed between adjacent metal electrodes using only low resolution patterning of the metal electrodes themselves. We have published the design of a tool to do this at https://doi.org/10.17863/CAM.68204 . However, to make an electronic device such as a transistor, we need to put materials into the gap between these metal electrodes.
Nanomaterials, such as carbon nanotubes, silicon nanowires, zinc oxide nanowires and graphene, have been shown to have exceptional intrinsic electronic properties as a result of their nanostructure. However, the challenge is usually to put metal electrodes onto these materials to be able to make use of these properties.
In this work, we propose to develop the manufacturing processes to bring together A-Lith nanogap manufacture with the bottom-up growth of these nanomaterials so that they naturally grow across the nanogap to make a new generation of electronic devices at low cost. Two such 'nanomaterial-in-nanogap' devices which we will demonstrate are transistors and memristors. The former have been the building block behind traditional electronic circuits. The latter are seen as the building block behind the neuromorphic electronics of the future, where we create electronic devices which take inspiration from the synapses of the brain to operate.
This project aims to bring the manufacture of these new nanomaterial-in-nanogap devices for large-area electronics to reality.
Publications
Bestelink E
(2024)
Promoting Low-Voltage Saturation in High-Performance a-InGaZnO Source-Gated Transistors
in IEEE Transactions on Electron Devices
Wyatt-Moon G
(2023)
Nanodiodes on a Digestible Substrate
| Description | This work is looking to develop a new generation of nanomaterial-in-nanogap (n-i-n) electronic devices that can be fabricated at very low cost over large areas. A multitude of promising electronic nano materials have emerged in recent years including zinc oxide nanowires, carbon nanotubes and graphene. However, a major challenge is integrating these materials into a complete semiconductor device process. Very expensive techniques like e-beam lithography are frequently needed where nanomaterials are grown on a surface in an uncontrolled way, they are then located by electron microscopy, and finally e-beam lithography is used to add contacts to these materials to make a device. This is expensive, time-consuming, and ultimately not scalable. We have been developing a novel high resolution patterning technique called adhesion lithography (a-lith) which allows coplanar electrodes of dissimilar metals to be produced with a gap length of ~10 nm between the electrodes, but while using a simple photolithorphy patterning technique. This is achieved by depositing first metal on a substrate and patterning using photolithography. This metal is then coated in a self-assembled monolayer (SAM) which acts like a non-stick coating. A second metal is deposited over the first and patterned with photolithography as well. The second metal can then be selectively peeled away from above the first to leave the coplanar electrode structure. The significant novelty in this project is that we have demonstrated an ability to directly grow zinc oxide nanowires between the electrodes across the 10 nm gap. This has two major advantages. First is the removement of a need to pattern the nanomaterial. Is grows selectively where it is useful - between the metal electrodes. This means that the process is scalable to large areas. Secondly, the minimal volume of nanomaterial in the gap means that there a a very small probability of finding a defect, and so the intrinsic properties of the nanomaterial can be realised. We have shown this for ZnO nanowires and have extensively compared the resulting devices against ZnO thin fins, with significant improvement in device performance demonstrated for a more simple fabrication process. We have been developing memristors based on the nanogap structure and are learning about the challenges and opportunities that this presents. We have also been able to unexpected work on understanding the physics of conduction in amorphous materials occupying the nano gap which is about to be published. |
| Exploitation Route | This work will be of interest to companies in the semiconductor industry who wish to use nanomaterials in future generations of devices. There are two aspects to this. One is the process development: we have made significant advances in widening the adhesion lithography process to allow a very much wider range of materials as contacts. The second is in the physics of nanogap devices. This could be taken forward thought the development of new devices and processes, including by UK-based companies as there is no need to use high end semiconductor fabrication facilities. |
| Sectors | Electronics Energy Manufacturing including Industrial Biotechology |