Low Dimensional Electronic Device Fabrication at Low Cost over Large Areas: Follow-on

Lead Research Organisation: University of Cambridge
Department Name: Engineering

Abstract

Over the last 40 years, we have seen a transformation in how we use electronic devices in our everyday lives from the emergence of home computing in the 1980s with occasional 'dial-up' connection of a single device in the home to the internet. In contrast, today we have a plethora of smart devices such as televisions, speakers, white goods, central heating and even doorbells all continuously connected to the internet through high speed broadband in addition to our mobile phones, tablets and personal computers. This trend will continue, with smart packaging, ubiquitous environmental monitoring, wearable wellbeing monitors amongst other emerging technologies becoming commonplace. The development of this 'Internet of Things' portents new manufacturing challenges. Silicon-based electronics has developed over this time based on trying to minimise the cost per transistor in electronic components such as microprocessors. In this way, microprocessors can be fabricated with billions of transistors at an affordable cost point. However, it is just not appropriate to use silicon-based electronics for all of these emerging applications because of cost, form factor, environmental and other limitations.
Large-area electronics (LAE) is the field which sees the use of new materials and processes to make electronics where the cost per unit area is minimised rather than the cost per device. Displays are perhaps the best known example of LAE, where a layer of electronics sits over an entire screen controlling the light output from each pixel, but other areas are emerging, and in particular the development of basic microprocessors, memories and logic on substrates such as flexible plastics which have radically different form factors from silicon. Also, as the cost of manufacture is much lower than for silicon-based electronics, manufacturing in the UK is a reality.
As with silicon, decreasing the physical size of LAE devices leads to performance enhancements, and these will be needed for future generations of smart technologies. but in general the cost of manufacture increases as feature size is reduced, and this makes fabrication at the nanoscale prohibitively expensive. We have been working on a patterning technique called Adhesion Lithography (A-Lith). This allows the reproducible fabrication of gaps ~10 nm in length to be formed between adjacent metal electrodes using only low resolution patterning of the metal electrodes themselves. We have published the design of a tool to do this at https://doi.org/10.17863/CAM.68204 . However, to make an electronic device such as a transistor, we need to put materials into the gap between these metal electrodes.
Nanomaterials, such as carbon nanotubes, silicon nanowires, zinc oxide nanowires and graphene, have been shown to have exceptional intrinsic electronic properties as a result of their nanostructure. However, the challenge is usually to put metal electrodes onto these materials to be able to make use of these properties.
In this work, we propose to develop the manufacturing processes to bring together A-Lith nanogap manufacture with the bottom-up growth of these nanomaterials so that they naturally grow across the nanogap to make a new generation of electronic devices at low cost. Two such 'nanomaterial-in-nanogap' devices which we will demonstrate are transistors and memristors. The former have been the building block behind traditional electronic circuits. The latter are seen as the building block behind the neuromorphic electronics of the future, where we create electronic devices which take inspiration from the synapses of the brain to operate.
This project aims to bring the manufacture of these new nanomaterial-in-nanogap devices for large-area electronics to reality.