Resilient and Testable Energy-Efficient Digital Hardware

The UK is home to some world-leading electronic companies including semiconductor IP supplier of low-power microprocessors (ARM), multimedia and communications cores (Imagination Technologies); which are at the heart of today's and future consumer electronics, and home entertainment. Power management is an essential enabling technology in such electronics and will become more prominent in future electronic systems. The downside of power management is that it decreases the reliability and increase the testability cost of energy-efficient hardware as demonstrated by recent academic and industrial research including that reported by the investigation team. This is because energy-efficient hardware often have no provision for tolerating run-time soft errors (unless for safety critical applications); and current methods for testing such hardware for manufacturing defects don't explicitly target power management circuitry. There are currently no fault models or test methods for power distribution networks and power management circuitry and no on-line soft error monitoring and correction methods for power management hardware. This grant application is focused on developing new fault models, methods, circuits and their validation (simulation, FPGA and AISC) to quantify and improve the resilience and testability of energy-efficient digital hardware. Particular emphasis is placed upon cost-effectiveness through joint consideration of reliability, and test and re-using on-chip hardware to minimise silicon area, power consumption and impact on functional performance. This is a three-year project involving two post-doctoral researchers (one for three years and the other for two years), and ARM (Cambridge) as an industrial partner. The project will be carried out in collaboration with Prof. F. Kurdahi (Uni. of California, Irvine) and Prof. M. Tehranipoor (Uni. of Connecticut). Both acknowledged world experts in the proposed research.

This project will significantly advance the present state-of-the-art in reliable and testable energy-efficient hardware and will lead to the following research deliverables:
1. New fault models for power management circuitry and power distribution network (PDMC) to underpin their logic and timing behaviour due to soft errors and manufacturing defects;
2. New methods and circuits and their practical validation for improving testability and diagnosis (against manufacturing defects) and reliability (against soft errors) through online monitoring and correction.
3. A design automation methodology for embedding automatically into an energy-efficient design the required circuitry to enable enhanced reliability and testability using existing EDA tools.

Impact on Knowledge: There are currently no fault models or test methods for power distribution networks and power management circuitry and no on-line soft error monitoring and correction methods for power management hardware. This research will provide high academic impact through significant advances in the present state-of-the-art design methods and automation of energy-efficient digital hardware. This will further raise the profile and presence of our internationally-leading research energy-efficient and dependable hardware by disseminating research results through high impact publications, organization of workshops, and giving invited talks at major international conferences.

Impact on the Economy: The microelectronics industry is highly competitive, particularly for consumer products. To remain ahead of the field it is important for companies to continually develop and improve their products, with a drive towards increased energy efficiency and reliability at reduced cost. The importance of the proposed research is derived from its contribution to ensure future hardware is low-power and dependable across a range of application areas from healthcare and transport to electronics design and safety critical systems. This research will demonstrate the potential of developing new fault models, methods and circuits, to design resilient and testable energy-efficient digital hardware, which will be highly attractive for commercial development. We believe that this proposal has two key areas of novelty that offer opportunities for exploitation. The first area is associated with developing soft-error and manufacturing-defects aware fault-models for power distribution networks and power management circuitry. The second area of is the methods and circuits together with the fault models will help to establish the scientific foundation required for the development of design flows and synthesis tools to support dependable and testable energy-efficient hardware. At present, there are no commercial tools for reliable and yield-aware low-power designs; therefore the research results will be attractive for commercial development. Exploitable results arising from the research will be dealt with through the University of Southampton Research and Innovation Services, and where appropriate (e.g. a start-up company). The project will directly benefit the project industrial partner ARM (Cambridge); market leaders in the design of low-power IP cores processors for consumer electronics. They fully appreciate the advantages of the developed methods, circuits and tools, which support the design of future energy-efficient computing platform.

Impact on People: The research programme will provide high-quality and industry-relevant training in the general area of Electronics Design and EDA tools to the two named research fellows and the opportunity to further increase their international research presence and leadership; improving their employability prospects.

Impact on Society: The School of Electronics and Computer Science (ECS) places a high value on communicating its research through media. It has its own experienced Marketing and Communications Manager, Joyce Lewis, responsible for all corporate marketing communications, public relations and media liaison. Joyce set up the ECS video podcasting news service in 2006, which was the first one in any UK academic institution. The video podcasts are a regular feature of our communications programme. Over the last five years, Joyce organised a large-scale media training programmes for postgraduate students and researchers, with over 100 people taking part. ECS issues around 80 news releases each year to international and national media and receives outstanding coverage. High quality media training of researchers is recognized as being an essential part of ECS success in public engagement, and is provided by a numnumber of experienced journalist trainers.