Meeting the design challenges of the nano-CMOS electronics

Lead Research Organisation: University of Glasgow
Department Name: School of Engineering

Abstract

The years of 'happy scaling' are over and the fundamental challenges that the semiconductor industry faces, at both technology and device level, will impinge deeply upon the design of future integrated circuits and systems. This proposal brings together semiconductor device, circuit and system experts from academia and industry and e-scientists with strong grid expertise. Only by working in close collaboration, and adequately connected and resourced by e-science and Grid technology, can we understand and tackle the design complexity of nano-CMOS electronics, securing a competitive advantage for the UK electronics industry.Increasing variability in device characteristics and the need to introduce novel device architectures represent major challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits. This will in turn demand revolutionary changes in the way in which future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate this increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designers. This can only be achieved by embedding e-science technology and know-how across the whole nano-CMOS electronics design process and revolutionising the way in which these disparate groups currently work.This project's over-arching aim is to revolutionise existing nano-CMOS electronics research processes by developing the methodology and prototype technology of a nano-CMOS Design Grid. We use the term Grid to encompass computing technologies that allow distributed groups to collaborate by sharing designs, simulations, workflows, data sets and computation resources. This work will require a deep understanding of how electronics scientists, engineers and designers can work together to produce new methods and results. Through this process we will create Grid-savvy nano-CMOS e-Researchers able to Grid-enable their own simulations, to correctly annotate their own data, to design workflows reflecting their design processes, and share all these with other researchers in the nano-CMOS design space.

Publications

10 25 50
 
Description Understanding and simulation of CMOS variability
Exploitation Route Provided IP for the creation of Gold Standard Simulations, LTD
Sectors Electronics

 
Description Provided IP for the creation of Gold Standard Simulations, Ltd
First Year Of Impact 2010
Sector Electronics
 
Description EPSRC
Amount £727,166 (GBP)
Funding ID EP/G04130 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Academic/University
Country United Kingdom of Great Britain & Northern Ireland (UK)
Start  
 
Description EPSRC
Amount £727,166 (GBP)
Funding ID EP/G04130 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Academic/University
Country United Kingdom of Great Britain & Northern Ireland (UK)
Start  
 
Description EPSRC
Amount £454,906 (GBP)
Funding ID EP/H024107/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Academic/University
Country United Kingdom of Great Britain & Northern Ireland (UK)
Start  
 
Description EPSRC
Amount £454,906 (GBP)
Funding ID EP/H024107/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Academic/University
Country United Kingdom of Great Britain & Northern Ireland (UK)
Start  
 
Description EPSRC
Amount £1,218,409 (GBP)
Funding ID GR/E038344/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Academic/University
Country United Kingdom of Great Britain & Northern Ireland (UK)
Start  
 
Description European Commission (EC)
Amount £400,000 (GBP)
Funding ID FP7 
Organisation European Commission 
Sector Public
Country European Union (EU)
Start  
 
Description European Commission (EC)
Amount £400,000 (GBP)
Funding ID FP7 
Organisation European Commission 
Sector Public
Country European Union (EU)
Start  
 
Description European Commission (EC)
Amount £318,231 (GBP)
Funding ID EU No. 216537 
Organisation European Commission 
Sector Public
Country European Union (EU)
Start  
 
Description European Commission (EC)
Amount £416,168 (GBP)
Funding ID FP7 
Organisation European Commission 
Sector Public
Country European Union (EU)
Start  
 
Description European Commission (EC)
Amount £318,231 (GBP)
Funding ID EU No. 216537 
Organisation European Commission 
Sector Public
Country European Union (EU)
Start  
 
Description European Commission (EC)
Amount £416,168 (GBP)
Funding ID FP7 
Organisation European Commission 
Sector Public
Country European Union (EU)
Start  
 
Description Scottish Enterprise Glasgow
Amount £70,000 (GBP)
Funding ID ENIAC 
Organisation Scottish Enterprise 
Sector Public
Country United Kingdom of Great Britain & Northern Ireland (UK)
Start  
 
Description Scottish Enterprise Glasgow
Amount £70,000 (GBP)
Funding ID ENIAC 
Organisation Scottish Enterprise 
Sector Public
Country United Kingdom of Great Britain & Northern Ireland (UK)
Start