Variation-Aware Test for NanoScale CMOS Integrated Circuits

Lead Research Organisation: University of Southampton
Department Name: Electronics and Computer Science

Abstract

Semiconductor manufacturing test is affected by fabrication process and power supply voltage (PV) variation as demonstrated recently by the investigating team. Performing test using existing methods and without considering PV varaition will lead to defects being missed by during test leading to reduced yield and reliability of integrated circuits. This grant application is focused on exploring and developing new and efficient test methods capable of mitigating the impact of PV variation leading to improved test quality and higher dependability. This project will provide significant advances in the present state-of-the-art semiconductor test and will help to establish the scientific foundation required for the development of next generation PV variation-aware test methods and tools for nanoscale integrated circuits. This includes new fault models for resistive open and resistive short defects that capture PV variation; accurate metrics for assessing and quantifying the impact of such variation on the quality and cost of test, and two variation-aware test pattern generation methods (logic and delay) capable of mitigating test escapes due to PV variation and efficient in terms of defect coverage and volume of test data. The developed models, metrics, and test generation methods will be evaluated using comprehensive simulation with nano-meter synthesized benchmark circuits and real-life test problem provided by the project industrial partner. This is a three-year project involving one named post doctoral researcher and one PhD student. The project will be carried out in collaboration with ARM (Cambridge) and Synopsys (US), and in collaboration with Prof. K. Chakrabarty (Duke Uni.), and Prof. S. Kundu (Uni. of Massachusetts) as visiting researchers.The research we propose is aligned with the EPSRC signposted Grand Challenges in microelectronics design as identified by the EPSRC network grant Developing a Common Vision for UK Research in Microelectronic Design . This proposal is aligned in particular with GC3 (More for Less: Performance-driven design for next generation chip technology), where one of the main technical issues that need to be addressed in this GC is Test and Verification if the semiconductor industry is to continue to produce more efficient designs with better performance, lower power and lower test and verification cost.

Publications

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Khursheed S (2014) Delay Test for Diagnosis of Power Switches in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Khursheed S (2010) Gate-Sizing-Based Single $V_{\rm dd}$ Test for Bridge Defects in Multivoltage Designs in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Shida Zhong (2011) A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Shida Zhong (2014) Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Yang S (2011) Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Yang S (2013) Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation in IEEE Transactions on Circuits and Systems I: Regular Papers

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Zhao Y (2015) Online Fault Tolerance Technique for TSV-Based 3-D-IC in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

 
Description Electronic chips used in mobile digital devices are extremely complex and to reduce their production cost and subsequently the cost of digital devices, there is continuing research to reduce further the cost of testing electronic chips and to improve their reliability. Our research developed new computer models and new testing methods for electronic chips manufactured using extremely small dimensions transistors.
Exploitation Route Our findings are being used already by the companies (ARM, Synopsys) that collaborated with us on the project, in developing cost effective test solutions (hardware and software) to complex electronic chips.
Sectors Electronics

 
Description Our findings are being used already by the companies (ARM and Synopsis) that collaborated with us on the project in development of cost effective test solutions (hardware and software) to complex electronic chips. Our research findings have been used by other researchers and academics in Europe, Asia and the US, to advance knowledge in the field. Our findings have also been used by industry particularly in the UK through our existing collaborative arrangements with ARM.
First Year Of Impact 2011
Sector Electronics
Impact Types Societal